To make I/O assignments, click and drag the REFCLK pin from the Schematic View to the pin location you desire in the Graphical Placement View. If the assignment is legal (no DRC violations), green lines appear to denote the accepted connection between the REFCLK pin through the Q(x)_TXPLL_SSC to the Transceiver lanes.
Figure 9-17. Legal and Accepted Reference Clock I/O Assignment
If the I/O assignment violates the DRC rule, the assignment is not
accepted. Red arrows denotes DRC violations. The following figure shows two illegal
assignments:
From the Reference Clock (REFCLK) to the Lanes (Red arrow from
REFCLK to the Q2_Lane0)
From the Transmit PLL to the lanes (Red arrow from TXPLL_SSC to
Q2_Lane0)
Figure 9-18. Illegal I/O Assignment
An error message appears in the Log window to identify the DRC rules
violated. In this case, there is no feasible dedicated connection from the REFCLK to the
Lane and from the Transmit PLL to the Lanes.Figure 9-19. Log Window Message
Note: I/O assignments can be made for REFCLK,
TXPLL, and Transceiver Lanes for all Transceiver protocols except the PCIe Protocol. For
the PCIe Protocol, Transceiver Lanes are assigned to predefined locations and cannot be
removed.
