9.9.2.2 Netlist Viewer—Flat

This is the flattened (non-hierarchical) netlist generated after synthesis, technology mapping and further optimization based on the DRC rules of the device family and/or die. Click on the Canvas to load the "Flat" view in the Netlist Viewer—Flat window. The Chip Planner loads the netlist into the system memory and displays it in the window as shown in the following figure.