21.6.21 SYNTHESIZE

Description

"SYNTHESIZE" is a command tool used in configure_tool and run_tool. Configure_tool is a general purpose Tcl command that allows you to configure a tool’s parameters and values prior to executing the tool. Configure tool then executes the specified tool with the configured parameters with run_tool command.

configure_tool -name {SYNTHESIZE} [-params {name:value}]
run_tool -name {SYNTHESIZE}

Arguments


Parameter	Type	Description
CLOCK_ASYNC	integer	Specifies the threshold value for asynchronous pin promotion to a global net. The default is 12.
CLOCK_GLOBAL	integer	Specifies the threshold value for Clock pin promotion. The default is 2.
CLOCK_DATA	integer	Specifies the threshold value for data pin promotion.The default is 5000. The possible values are integer values between 1000 and 200,000.
RAM_OPTIMIZED_FOR_POWER	boolean	Set to true or 1 to optimize RAM for Low Power; RAMS are inferred and configured to ensure the lowest power consumption. Set to false or 0 to optimize RAM for High Speed at the expense of more FPGA resources. The possible values are boolean {true \| false \| 1 \| 0}.
RETIMING	boolean	Set to true or 1 to enable Retiming during synthesis. Set to false or 0 to disable Retiming during synthesis. The possible values are boolean {true \| false \| 1 \| 0}.
SYNPLIFY_OPTIONS	string	Specifies additional synthesis-specific options. Options specified by this parameter override the same options specified in the user Tcl file if there is a conflict.
SYNPLIFY_TCL_FILE	string	Specifies the absolute or relative path name to the user Tcl file containing synthesis-specific options.
BLOCK_MODE	boolean	Set to true or 1 when you have blocks in your design and you want to enable the Block mode. Set it to false or 0 if you don’t have blocks in your design. Default is false or 0. The possible values are boolean {true \| false \| 1 \| 0}.
BLOCK_PLACEMENT_CONFLICTS	string	Instructs the COMPILE engine what to do when the software encounters a placement conflict. When set to: ERROR - Compile errors out if any instance from a Designer block becomes unplaced. This is the default.KEEP - If some instances get unplaced for any reason, the non-conflicting elements remaining are preserved but not locked. Therefore, the placer can move them into another location if necessary. LOCK- If some instances get unplaced for any reason, the non-conflicting elements remaining are preserved and locked.DISCARD – Discards any placement from the block,even if there are no conflicts. The possible values are {ERROR \| KEEP \| LOCK \| DISCAR D}.
BLOCK_ROUTING_CONFLICTS	string	Instructs the COMPILE engine what to do when the software encounters a routing conflict. When set to: ERROR - Compile errors out if any route in any preserved net from a Designer block is deleted. This is the default. KEEP – If a route is removed from a net for any reason, the routing for the non-conflicting nets is kept unlocked. The router can re-route these nets. LOCK – If routing is removed from a net for any reason, the routing for the non- conflicting nets is kept as locked, and the router will not change them. DISCARD - Discards any routing from the block,even if there are no conflicts. The possible values are {ERROR \| KEEP \| LOCK \| DISCAR D}.
PA4_GB_COUNT	integer	The number of available global nets is reported. Minimum for all dies is “0”. Default and Maximum values are die-dependent: 005/010 die: Default =Max = 8 025/050/060/090/150 die: Default=Max=16 RT4G075/RT4G150: Default=24, Max=48.Note: For RTG4, default is 48.
PA4_GB_MAX_RCLKINT_INSERTION	integer	Specifies the maximum number of global nets that could be demoted to row-globals. Default is 16, Minis 0 and Max is 50.
PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT	integer	Specifies the Minimum fanout of global nets that could be demoted to row-globals. Default is 300.Min is 25 and Max is 5000.
LANGUAGE_SYSTEM_VLOG	boolean	Set to true if the Verilog files contain System Verilog constructs. The possible values are boolean {true \| false}.
LANGUAGE_VERILOG_2001	boolean	Set to true if Verilog files contain Verilog 2001 constructs. The possible values are boolean {true \| false}.
CDC_MIN_NUM_SYNC_REGS	integer	Minimum number of synchronizer registers. Range: 2 - 9. Default: 2
CDC_REPORT	boolean	The generated CDC report will not contain any synchronizer circuits formed with macros instantiated from the catalog. The generated report, with the name `<root_name>_cdc.csv`, will be visible in the respective Synthesis node of the report view. The report contains all CDC inferred from the RTL design and explains the reason(s) why a synchronizer is considered unsafe. The possible values are boolean {true \| false}.


Return Type	Description
Integer	Both for "configure_tool -name {SYNTHESIZE}" and "run_tool -name {SYNTHESIZE}" returns 0 on success and 1 on failure.

Error Codes


Error Code	Description
None	Parameter 'params' has illegal value.
None	Required parameter 'params' is missing.
None	Parameter 'name' has illegal value.
None	Parameter 'param_name' is not defined. Valid command formatting is 'configure_tool -name "tool name" [-params "params"]+'.
None	RETIMING is set to an illegal value value. Legal value are true, false, 0 or 1.
None	RETIMING has no value. Legal values are true, false, 0 or 1.
None	RAM_OPTIMIZED_FOR_POWER is set to an illegal value value. Legal value are true, false, 0 or 1.
None	RAM_OPTIMIZED_FOR_POWER has no value. Legal values are true, false, 0 or 1.
None	PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT is set to an illegal value value. Legal value must be between 25 and 5000.
None	PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT has no value. Legal value must be between 25 and 5000.
None	PA4_GB_MAX_RCLKINT_INSERTION has no value. Legal value must be between 0 and 50.
None	CLOCK_GLOBAL is set to an illegal value value. Legal value must be between 2 and 200000.
None	CLOCK_GLOBAL has no value. Legal value must be between 2 and 200000.
None	CLOCK_DATA is set to an illegal value value. Legal value must be between 1000 and 200000.
None	CLOCK_DATA has no value. Legal value must be between 1000 and 200000.
None	CLOCK_ASYNC is set to an illegal value value. Legal value must be between 12 and 200000.
None	CLOCK_ASYNC has no value. Legal value must be between 12 and 200000.
None	BLOCK_ROUTING_CONFLICTS is set to an illegal value value. Legal values for BLOCK_ROUTING_CONFLICTS are ERROR, LOCK, KEEP and DISCARD.
None	BLOCK_ROUTING_CONFLICTS has no value. Legal values for BLOCK_ROUTING_CONFLICTS are ERROR, LOCK, KEEP and DISCARD.
None	BLOCK_PLACEMENT_CONFLICTS is set to an illegal value value. Legal values for BLOCK_PLACEMENT_CONFLICTS are ERROR, LOCK, KEEP and DISCARD.
None	BLOCK_PLACEMENT_CONFLICTS has no value. Legal values for BLOCK_PLACEMENT_CONFLICTS are ERROR, LOCK, KEEP and DISCARD.
None	BLOCK_MODE is set to an illegal value value. Legal value are true, false, 0 or 1.

Supported Families


Supported Families
PolarFire®
PolarFire SoC
RTG4™
SmartFusion® 2
IGLOO® 2

Example

Configure "SYNTHESIZE" tool and run.

configure_tool -name {SYNTHESIZE} \ -params {BLOCK_MODE:false} \ 
               -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} \
               -params {BLOCK_ROUTING_CONFLICTS:ERROR} \
               -params {CLOCK_ASYNC:12} -params {CLOCK_DATA:5010} \
               -params {CLOCK_GLOBAL:2} \
               -params {PA4_GB_MAX_RCLKINT_INSERTION:16} \
               -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:299} \
               -params {RAM_OPTIMIZED_FOR_POWER:false} \
               -params {RETIMING:false} \
               -params {SYNPLIFY_TCL_FILE:./test.tcl} \
               -params {SYNPLIFY_OPTIONS:set_option \
               -run_prop_extract 1;
               set_option -maxfan 10000;
               set_option -clock_globalthreshold 2;
               set_option -async_globalthreshold 12;
               set_option -globalthreshold 5000;
               set_option -low_power_ram_decomp 0;}

run_tool -name {SYNTHESIZE}

To configure Synthesis tool for adding the IDC file:

configure_tool -name {SYNTHESIZE} -params {ACTIVE_IMPLEMENTATION:synthesis}
-params {CREATE_IMPLEMENTATION_IDENTIFY:Synthesis_Jan27_N} -params
{SYNPLIFY_OPTIONS:} -params {SYNPLIFY_TCL_FILE:D:/Syn_27.tcl}

Where Syn_27.tcl script contains the following given command for adding IDC file:


set_option -ident_constraint  D:/MK.idc