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Libero SoC Design Suite Help Documentation
Libero SoC Design Suite Help Documentation
  1. Home
  2. 21 Tcl Command Reference

    Information about Tcl Command Reference

  3. 21.3 Project Manager Tcl Commands

  • 1 What's New

    Information about what is new in Libero SoC Design Suite

  • 2 Download Help

    Information to help you download the Libero SoC Design Suite documentation

  • 3 SmartHLS Compiler

    Information about SmartHLS Compiler

  • 4 Installation and Licensing

    Information about Libero SoC software installation and licensing

  • 5 Design Flow

    Information about Design Flow

  • 6 Block Flow

    Information about Block Flow

  • 7 SmartDesign

    Information about SmartDesign

  • 8 Netlist Viewer

    Information about Netlist Viewer

  • 9 I/O Editor

    Information about I/O Editor

  • 10 PDC Commands

    Information about PDC commands for all families

  • 11 Chip Planner

    Information about Chip Planner

  • 12 Timing Constraints Editor

    Information about Timing Constraints Editor

  • 13 SmartTime Static Timing Analyzer

    Information about SmartTime Static Timing Analyzer

  • 14 SmartPower

    Information about SmartPower

  • 15 Programming and Debugging

    Information about Programming and Debugging

  • 16 Macro Library

    Information about Macro Library for SmartFusion2, IGLOO2 and PolarFire

  • 17 Custom Flow

    Information about Custom Flow

  • 18 Design Separation Methodology

    Information about Design Separation Methodology

  • 19 Microchip Separation Verification Tool

    Information about Microchip Separation Verification Tool

  • 20 PolarFire SoC Microcontroller Subsystem (MSS)

    Information about PolarFire SoC Microcontroller Subsystem (MSS)

  • 21 Tcl Command Reference

    Information about Tcl Command Reference

    • 21 Introduction
    • 21.1 Tcl Scripting Overview
    • 21.2 Building a Libero Design Using Tcl
    • 21.3 Project Manager Tcl Commands
      • 21.3.1 add_file_to_library

      • 21.3.2 add_library
      • 21.3.3 add_modelsim_path

      • 21.3.4 add_profile
      • 21.3.5 associate_stimulus

      • 21.3.6 build_design_hierarchy

      • 21.3.7 change_link

      • 21.3.8 change_all_links

      • 21.3.9 change_vault_location

      • 21.3.10 check_fdc_constraints

      • 21.3.11 check_hdl

      • 21.3.12 check_ndc_constraints

      • 21.3.13 check_pdc_constraints
      • 21.3.14 check_sdc_constraints
      • 21.3.15 cleanall_tool

      • 21.3.16 close_design
      • 21.3.17 close_project
      • 21.3.18 configure_core
      • 21.3.19 create_and_configure_core

      • 21.3.20 configure_tool
      • 21.3.21 create_links

      • 21.3.22 create_set

      • 21.3.23 create_smartdesign

      • 21.3.24 delete_component

      • 21.3.25 delete_files

      • 21.3.26 download_core

      • 21.3.27 download_latest_cores

      • 21.3.28 edit_profile
      • 21.3.29 edit_post_layout_design

      • 21.3.30 export_as_link
      • 21.3.31 export_ba_files

      • 21.3.32 export_bitstream_file
      • 21.3.33 export_bsdl_file

      • 21.3.34 export_component_to_tcl

      • 21.3.35 export_design_summary

      • 21.3.36 export_firmware
      • 21.3.37 export_fp_pdc

      • 21.3.38 export_ibis_file

      • 21.3.39 export_interrupt_map
      • 21.3.40 export_io_pdc

      • 21.3.41 export_job_data

      • 21.3.42 export_netlist_file

      • 21.3.43 export_parameter_report

      • 21.3.44 export_pin_reports
      • 21.3.45 export_profiles

      • 21.3.46 export_prog_job

      • 21.3.47 export_script
      • 21.3.48 export_sdc_file
      • 21.3.49 export_smart_debug_data

      • 21.3.50 force_update_design_flow

      • 21.3.51 generate_component
      • 21.3.52 generate_sdc_constraint_coverage
      • 21.3.53 get_libero_release

      • 21.3.54 get_libero_version

      • 21.3.55 get_tool_options

      • 21.3.56 get_tool_state

      • 21.3.57 import_component
      • 21.3.58 import_component_data
      • 21.3.59 import_files
      • 21.3.60 import_mss_component

      • 21.3.61 is_synthesis_enabled
      • 21.3.62 new_project
      • 21.3.63 one_way_passcode
      • 21.3.64 open_project

      • 21.3.65 open_smartdesign

      • 21.3.66 organize_constraints

      • 21.3.67 organize_sources

      • 21.3.68 organize_tool_files

      • 21.3.69 project_general_settings

      • 21.3.70 project_settings

      • 21.3.71 publish_block

      • 21.3.72 refresh

      • 21.3.73 remove_core

      • 21.3.74 remove_library

      • 21.3.75 remove_profile

      • 21.3.76 rename_file

      • 21.3.77 rename_library

      • 21.3.78 run_tool

      • 21.3.79 save_log

      • 21.3.80 save_project

      • 21.3.81 save_project_as
      • 21.3.82 save_smartdesign

      • 21.3.83 select_profile

      • 21.3.84 set_actel_lib_options

      • 21.3.85 set_active_testbench
      • 21.3.86 set_as_target

      • 21.3.87 set_device

      • 21.3.88 set_global_include_file

      • 21.3.89 set_global_include_path_order

      • 21.3.90 set_modelsim_options
      • 21.3.91 set_option

      • 21.3.92 set_root

      • 21.3.93 set_user_lib_options

      • 21.3.94 smartdesign

      • 21.3.95 unlink_copy_locally

      • 21.3.96 unlink_files

      • 21.3.97 unset_as_target

      • 21.3.98 unset_global_include_file

      • 21.3.99 update_component_version

      • 21.3.100 use_source_file

      • 21.3.101 update_and_run_tool
    • 21.4 SmartDesign Tcl Commands
    • 21.5 HDL Tcl Commands
    • 21.6 Command Tools
    • 21.7 MSS Tcl Commands
    • 21.8 SmartTime Tcl Commands
    • 21.9 SmartPower Tcl Commands
    • 21.10 Programming and Configuration Tcl Commands
    • 21.11 FlashPro Express Tcl Commands
    • 21.12 Configure JTAG Chain Tcl Commands
    • 21.13 SmartDebug Tcl Commands
    • 21.14 System Builder Tcl Commands
    • 21.15 Simultaneous Switching Noise Analyzer (SSNA) Tcl Commands

    • 21.16 HSM Tcl Commands

    • 21.17 Derive Constraints Tcl Commands
  • 22 Additional Information

    Additional information about other Microchip products

  • 23 Technical Support
  • 24 About Microchip

    More information about Microchip

21.3 Project Manager Tcl Commands

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