13.17.7 Reference Oscillator x Control
Note:
- REFOCON.ROSEL must not be
written while the REFOCON.ACTIVE bit is ‘
1’ – This will result in undefined behavior. - REFOCON must not be written when REFOCON[ON] != REFOCON[ACTIVE] – This will result in undefined behavior.
- This register can always be accessed regardless of the cfg_sys_unlock value.
| Name: | REFOxCON |
| Offset: | 0x70 + (x-1)*0x20 [x=1..6] |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RODIV14 | RODIV13 | RODIV12 | RODIV11 | RODIV10 | RODIV9 | RODIV8 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RODIV7 | RODIV6 | RODIV5 | RODIV4 | RODIV3 | RODIV2 | RODIV1 | RODIV0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | FRZ | SIDL | OE | RSLP | DIVSW_EN | ACTIVE | |||
| Access | R/W | R/W | R/W | R/W | R/W | HC/ R/W | HS/HC/ R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ROSEL3 | ROSEL2 | ROSEL1 | ROSEL0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 – RODIV Reference Clock Divider bits
Specifies 1/2 period of reference clock in the source clocks.
Example: Period of refo_clk = [Reference source * 2] * RODIV
| Value | Description |
|---|---|
| 111111111111111 | REFOx clock is Base clock frequency divided by 65,534 (32,767 *2) |
| 111111111111110 | REFOx clock is Base clock frequency divided by 65,532 (32,766 * 2) |
| ... | |
| ... | |
| ... | |
| 000000000000011 | REFOx clock is Base clock frequency divided by 6 (3*2) |
| 000000000000010 | REFOx clock is Base clock frequency divided by 4 (2*2) |
| 000000000000001 | REFOx clock is Base clock frequency divided by 2 (1*2) |
| 000000000000000 | REFOx clock is same frequency as Base clock (no divider) |
Bit 15 – ON Output Enable bit
| Value | Description |
|---|---|
| 1 | Reference Oscillator Module is enabled |
| 0 | Reference Oscillator Module is disabled |
Bit 14 – FRZ Freeze in Debug mode bit
| Value | Description |
|---|---|
| 1 | When the emulator is in the Debug mode, module freezes operation |
| 0 | When the emulator is in the Debug mode, module continues operation |
Bit 13 – SIDL Peripheral Stop in Idle Mode bit
| Value | Description |
|---|---|
| 1 | Discontinues module operation when device enters the Idle mode |
| 0 | Continues module operation in the Idle mode |
Bit 12 – OE Reference Clock Output Enable bit
| Value | Description |
|---|---|
| 1 | Reference clock is driven out on REFOx pin |
| 0 | Reference clock is not driven out on REFOx pin |
Bit 11 – RSLP Reference Oscillator Run in Sleep bit
Note: This bit is ignored when ROSEL[3:0] = (0000 or 0001).
| Value | Description |
|---|---|
| 1 | Reference Oscillator output continues to run in the Sleep mode |
| 0 | Reference Oscillator output is disabled in the Sleep mode |
Bit 9 – DIVSW_EN Clock RODIV/ROTRIM switch enabled
| Value | Description |
|---|---|
| 1 | Clock Divider Switching is currently in progress |
| 0 | Clock Divider Switch has completed |
Bit 8 – ACTIVE Reference Clock Request Status bit
| Value | Description |
|---|---|
| 1 | Reference clock request is active (User must not update this REFOCON register) |
| 0 | Reference clock request is not active (User can update this REFOCON register) |
Bits 0, 1, 2, 3 – ROSEL Reference Clock Source Select bits
| Value | Description |
|---|---|
| 1001-1111 | Reserved |
| 1000 | REFI pin |
| 0111 | System clock (reference clock reflects any device clock switching) |
| 0110 | Peripheral clock (reference clock reflects any peripheral clock switching) |
| 0101 | System PLL (Clock-3) |
| 0100 | LPRC |
| 0011 | SOSC |
| 0010 | POSC |
| 0001 | System PLL (Clock-1) |
| 0000 | FRC |