13.17.1 CRU Oscillator Control

Note: The system unlock sequence must be done before this register can be written.
Name: OSCCON
Offset: 0x00
Reset: 0x00000000

Bit 3130292827262524 
      FRCDIV[2:0] 
Access R/W/LR/W/LR/W/L 
Reset 000 
Bit 2322212019181716 
 DRMEN 2SPDSLP      
Access R/W/LR/W/L 
Reset 01 
Bit 15141312111098 
 COSC[3:0]NOSC[3:0] 
Access RRRRR/W/LR/W/LR/W/LR/W/L 
Reset 00000000 
Bit 76543210 
 CLKLOCK  SLPENCF SOSCENOSWEN 
Access R/W/LR/W/LR/W/HS/LR/W/LR/W/HC/L 
Reset 00011 

Bits 26:24 – FRCDIV[2:0] Fast RC Clock Divider bits

ValueDescription
000FRC Divide by 1 (default value)
001FRC Divide by 2
010FRC Divide by 4
011FRC Divide by 8
100FRC Divide by 16
101FRC Divide by 32
110FRC Divide by 64
111FRC Divide by 256

Bit 23 – DRMEN Enable the Dream Mode bit

ValueDescription
1When the cpu has executed WFI instruction and SLPEN = 1, peripheral clock requests are NOT active causes to enter the Sleep mode
0DMA transfer has no effect

Bit 21 – 2SPDSLP 2-Speed Start-up enabled in the Sleep mode bit

Note: Default Reset Value is specified by cfg_two_speed_startup_en input.
ValueDescription
1When the device exits the Sleep Mode, the SYS_CLK will be from FRC until the selected clock is ready
0When the device exits the Sleep Mode, the SYS_CLK will be from the selected clock

Bits 15:12 – COSC[3:0] Current Oscillator Selection bits (Read-only)

Note:
  • The default value on Reset is 4’b0000, which ensures that a virgin die has frc_clk running for ICDJTAG or EJTAG to program the NVR.
  • Loaded with NOSC[3:0] at the completion of a successful clock switch.
  • Set to FRC value (0000) when FSCM detects a failure and switches clock to FRC.
ValueDescription
0000Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV
0001System PLL Clock-1 (SPLL1 Module) (input clock and divider set by SPLLCON)
0010Primary Oscillator (POSC)
0011Secondary Oscillator (SOSC)
0100Low Power RC Oscillator (LPRC)
0101-1111Reserved for future use

Bits 11:8 – NOSC[3:0] New Oscillator Selection bits

Note: Default value on Reset is 4’b0000, which ensures that a virgin die has frc_clk running for ICDJTAG or EJTAG to program the NVR.
ValueDescription
0000Fast RC Oscillator (FRC) divided by OSCCON.FRCDIV
0001System PLL Clock-1 (SPLL1 Module) (input clock and divider set by SPLLCON)
0010Primary Oscillator (POSC)
0011Secondary Oscillator (SOSC)
0100Low Power RC Oscillator (LPRC)
0101-1111Reserved for future use

Bit 7 – CLKLOCK Clock Lock Enabled bit

Note:
  • Once set, this bit can only be cleared via a Device Reset.
  • When active, this bit prevents writes to the following registers: NOSC[3:0] and OSWEN.
ValueDescription
1

All clock and PLL configuration registers are locked.

These include OSCCON, OSCTRIM, SPLLCON, UPLLCON, PBxDIV

0Clock and PLL selection registers are not locked, configurations may be modified.

Bit 4 – SLPEN Enable the Sleep Mode bit

ValueDescription
1When a WAIT Instruction is executed device will enter SLEEP Mode
0When a WAIT instruction is executed device will enter IDLE Mode

Bit 3 – CF Clock Fail Detect bit (Read/writable/Clearable by application)

Note:
  • Writing a ‘1’ to this bit will cause a clock switching sequence to be initiated by the clock switch state machine
  • Resets when a valid clock switching sequence is initiated by the clock switch state machine
  • This bit is set when clock fail event is detected
ValueDescription
1FSCM has detected clock failure
0FSCM has not detected clock failure

Bit 1 – SOSCEN 32 kHz Secondary (LP) Oscillator Enable bit

ValueDescription
1Enable Secondary Oscillator
0Disable Secondary Oscillator

Bit 0 – OSWEN Oscillator Switch Enable bit

Note:
  • A Write of value ‘0’ has no effect.
  • Cleared by hardware after a successful clock switch
  • Cleared by hardware after a redundant clock switch (NOSC = COSC)
  • Cleared by hardware after FSCM switches the oscillator to Fail-Safe Clock Source (FRC)
ValueDescription
1Request oscillator switch to selection specified by NOSC[3:0] bits
0Oscillator switch is complete