13.17.3 SPLL (RFPLL/Wrapper) Control

Note: The system unlock sequence must be done before these registers can be written.
Name: SPLLCON
Offset: 0x20
Reset: 0x00000000

Bit 3130292827262524 
 SPLL_BYP[1:0]       
Access R/W/LR/W/L 
Reset 11 
Bit 2322212019181716 
     SPLL2POSTDIV2[3:0] 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0001 
Bit 15141312111098 
 SPLL1POSTDIV1[7:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 00000000 
Bit 76543210 
   SPLLRSTSPLLFLOCKSPLLPWDN    
Access R/W/LR/W/LR/W/L 
Reset 101 

Bits 31:30 – SPLL_BYP[1:0] SPLL Bypass; when this bit is set, the input clock REF bypasses PLL to PLLOUTx.

Note:
  • Dictates clock source for ADC CP (Analog-to-Digital Converter Charge Pump) (SPLL2) Clock generation only
  • Clock source must be preselected and kept ready before the need of ADC CP arrives. Failure to do so will result in the loss of clock for one or two cycles when ADC CP is enabled.
ValueDescription
00RFPLL Clock is the clock source for ADC CP clock generation.
x1FRC is used as clock source for ADC CP clock generation.
10POSC is used as clock source for ADC CP clock generation.

Bits 19:16 – SPLL2POSTDIV2[3:0] ADC-CP Post Divide Value

ValueDescription
1 ≤ SPLLPOSTDIV2 ≤ 15Divide-by SPLLPOSTDIV2
0No Clock; Clock disabled

Bits 15:8 – SPLL1POSTDIV1[7:0] First Post Divide Value

ValueDescription
2 ≤ SPLLPOSTDIV ≤ 255Divide-by SPLLPOSTDIV
0Divide-by 1
1Divide-by 1.5

Bit 5 – SPLLRST System PLL Reset

ValueDescription
1Assert the Reset to the SPLL
0De-assert the Reset to the SPLL

Bit 4 – SPLLFLOCK System PLL Force Lock

ValueDescription
1Force the SPLL lock signal to be asserted
0Do not force the SPLL lock signal to be asserted

Bit 3 – SPLLPWDN PLL Power Down Register bit

ValueDescription
1PLL is powered down
0PLL is active