13.17.4 Reset Control Register
| Name: | RCON |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| POR_IO | POR_CORE | BCFGERR | BCFGFAIL | NVMLTA | NVMEOL | ||||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VBAT | |||||||||
| Access | R/W/HS | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DPSLP | CMR | ||||||||
| Access | R/W/HS | R/W/HS | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EXTR | SWR | DMTO | WDTO | SLEEP | IDLE | BOR | POR | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – POR_IO I/O Voltage POR Flag bit
Set by hardware at detection of an I/O POR event. User software must clear this bit to view next detection.
Note: User may write this bit to
‘
1’. Does not cause a POR_IO.| Value | Description |
|---|---|
| 1 | A Power-on Reset has occurred due to I/O voltage |
| 0 | A Power-on Reset has not occurred due to I/O voltage |
Bit 30 – POR_CORE Core Voltage POR Flag bit
Note: User may write this bit to
‘
1’. Does not cause a POR_CORE.| Value | Description |
|---|---|
| 1 | A Power-on Reset has occurred due to I/O voltage |
| 0 | A Power-on Reset has not occurred due to I/O voltage |
Bit 27 – BCFGERR BCFG Error Flag bit
A primary BCFG value had an error, but the secondary BCFG value was valid and used.
| Value | Description |
|---|---|
| 1 | A BCFG error has occurred |
| 0 | A BCFG error has not occurred |
Bit 26 – BCFGFAIL BCFG Failure Flag bit
Both the Primary and Secondary BCFG values had an unrecoverable error. Default values are in effect.
| Value | Description |
|---|---|
| 1 | A BCFG error has occurred |
| 0 | A BCFG error has not occurred |
Bit 25 – NVMLTA NVM Life Time Alert Flag bit
NVM Life Time Alert – Due to charge leakage, the NVM is nearing EOL.
| Value | Description |
|---|---|
| 1 | A NVM LTA error has occurred |
| 0 | A NVM LTA error has not occurred |
Bit 24 – NVMEOL NVM End of Life Flag bit
NVM End of Life – may not be visible to user, because the part will not come out of Reset if the bit is asserted.
| Value | Description |
|---|---|
| 1 | A NVM EOL failure has occurred |
| 0 | A NVM EOL failure has not occurred |
Bit 16 – VBAT VBAT Mode Flag bit
| Value | Description |
|---|---|
| 1 | A POR exit from VBAT has occurred. A true POR must be established with the valid VBAT voltage level on the VBAT pin. |
| 0 | A POR exit from VBAT has not occurred. |
Bit 10 – DPSLP Deep Sleep Mode Flag bit
| Value | Description |
|---|---|
| 1 | Deep Sleep mode has occurred |
| 0 | Deep Sleep mode has not occurred |
Bit 9 – CMR Configuration Mismatch Reset Flag bit
Note: User may write this bit to
‘
1’. Does not cause a Mismatch Reset.| Value | Description |
|---|---|
| 1 | A CMR event has occurred |
| 0 | A CMR event has not occurred |
Bit 7 – EXTR External Reset (MCLR) Status bit
Note: User may write this bit to
‘
1’. Does not cause a
(MCLR).| Value | Description |
|---|---|
| 1 | A Master Clear (pin) Reset has occurred |
| 0 | A Master Clear (pin) Reset not occurred |
Bit 6 – SWR Software Reset Flag bit
Note: User may write this bit to
‘
1’. Does not cause SWR.| Value | Description |
|---|---|
| 1 | A SWR has occurred |
| 0 | A SWR not occurred |
Bit 5 – DMTO Deadman Timer Time-out Flag bit
Note: User may write this bit to
‘
1’. Does not cause DMT Reset.| Value | Description |
|---|---|
| 1 | DMT Time-out has occurred and caused a Reset |
| 0 | DMT Time-out has not occurred |
Bit 4 – WDTO Watchdog Timer Time-out Flag bit
Note: User may write this bit to
‘
1’. Does not cause WDT Reset.| Value | Description |
|---|---|
| 1 | WDT Time-out has occurred and caused a Reset |
| 0 | WDT Time-out has not occurred |
Bit 3 – SLEEP Wake from Sleep Flag bit
Note: User may write this bit to
‘
1’. Does not invoke Sleep mode.| Value | Description |
|---|---|
| 1 | Device has been in Sleep mode |
| 0 | Device has not been in Sleep mode |
Bit 2 – IDLE Wake from Idle Flag bit
Note: User may write this bit to
‘
1’. Does not invoke Idle mode.| Value | Description |
|---|---|
| 1 | Device was in the Idle mode |
| 0 | Device was not in the Idle mode |
Bit 1 – BOR BOR Flag bit
Note: User may write this bit to
‘
1’. Does not cause a BOR.| Value | Description |
|---|---|
| 1 | A BOR has occurred |
| 0 | A BOR has not occurred |
Bit 0 – POR POR Flag bit
Note: User may write this bit to
‘
1’. Does not cause a POR.| Value | Description |
|---|---|
| 1 | A Power-on Reset has occurred |
| 0 | A Power-on Reset has not occurred |