13.17.6 NMI Control Register


Bit	31	30	29	28	27	26	25	24
							DMTO	WDTR
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	SWNMI				EXT	PLVD	CF	WDTS
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	15	14	13	12	11	10	9	8
	NMICNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	NMICNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 25 – DMTO Deadman Timer Time-out Flag bit (This will cause a Reset when NMICNT expires.)

Note: User may write this bit to ‘1’. Causes a user-initiated DMT NMI event and NMICNT start.

Value	Description
1	DMT Time-out has occurred and caused a NMI
0	DMT Time-out has not occurred

Bit 24 – WDTR Watchdog Timer Time-out in Run Flag bit

Note: User may write this bit to ‘1’. Causes a user-initiated WDT NMI event and NMICNT start.

Value	Description
1	WDT Time-out has occurred and caused an NMI (This may cause a Reset if NMICNT expires.)
0	WDT Time-out has not occurred

Bit 23 – SWNMI Software NMI Trigger bit

Value	Description
1	Writing a ‘`1`’ to this bit will cause an NMI to be generated
0	Writing a ‘`0`’ to this bit will have no effect

Bit 19 – EXT External / Generic NMI Event bit

Note: User may write this bit to ‘1’. Causes a user-initiated EXT NMI event.

Value	Description
1	A general NMI event was detected and caused an NMI. Writing ‘`0`’ to this bit will clear the NMI event
0	A general NMI event was not detected

Bit 18 – PLVD Programmable Low Voltage Detect Event bit

Note: User may write this bit to ‘1’. Causes a user-initiated PLVD NMI event.

Value	Description
1	PLVD detected a low voltage condition and caused an NMI
0	PLVD did not detect a low voltage condition

Bit 17 – CF Clock Fail Detect bit (Read/Clear-able by application)

Note: Writing a ‘1’ to the CF bit will cause a user-initiated clock failure NMI event, but will not actually cause a clock switch.

Value	Description
1	FSCM detected clock failure and caused an NMI
0	FSCM did not detect a clock failure

Bit 16 – WDTS Watch-Dog Timer Time-out in Sleep Flag bit

Note: User may write this bit to ‘1’. Causes a user-initiated WDT NMI event.

Value	Description
1	WDT Time-out has occurred during Sleep mode and caused a wake-up from sleep
0	WDT Time-out has not occurred during Sleep mode

Bits 15:0 – NMICNT[15:0] NMI Reset counter value bit

This bit field specifies the reload value used by the NMI Reset counter.

0000_0000_0000_0000 = No delay between NMI assertion and device Reset event
0000_0000_0000_0001
0000_0000_0000_0010
.................
.................
.................
1111_1111_1111_1110 
1111_1111_1111_1111 = Number of SYSCLK cycles that Software has to clear the NMI event before a device Reset is performed. If the NMI event is cleared before the counter reached zero, then NO device Reset is asserted.

Note: When a WDT NMI event occurs (when not in the Sleep mode), the NMICNT starts incrementing from the zero NMICNT value. When a DMT NMI event is triggered, the NMICNT starts decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset counter is only applicable to these two specific NMI events.

Name:	RNMICON
Offset:	0x50
Reset:	0x00000000
Property:	-