13.17.12 User Clock Diagnostics Control

Note: The system unlock sequence must be done before this register can be written.
Name: CLK_DIAG
Offset: 0x190
Reset: 0x00000000

Bit 3130292827262524 
 NMICTR15NMICTR14NMICTR13NMICTR12NMICTR11NMICTR10NMICTR9NMICTR8 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 NMICTR7NMICTR6NMICTR5NMICTR4NMICTR3NMICTR2NMICTR1NMICTR0 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  SPLL3_STOPSPLL2_STOPSPLL1_STOPLPRC_STOPFRC_STOPSOSC_STOPPOSC_STOP 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NMICTR Internal value of internal NMI Counter

This field reflects the actual value of the internal NMI counter

Bit 6 – SPLL3_STOP SPLL Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0SPLL3 clock source runs as normal
1SPLL3 clock source is stopped

Bit 5 – SPLL2_STOP SPLL Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0SPLL2 clock source runs as normal
1SPLL2 clock source is stopped

Bit 4 – SPLL1_STOP SPLL Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0SPLL1 clock source runs as normal
1SPLL1 clock source is stopped

Bit 3 – LPRC_STOP LPRC Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0LPRC clock source runs as normal
1LPRC clock source is stopped

Bit 2 – FRC_STOP FRC Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0FRC clock source runs as normal
1FRC clock source is stopped

Bit 1 – SOSC_STOP SOSC Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0SOSC clock source runs as normal
1SOSC clock source is stopped

Bit 0 – POSC_STOP POSC Clock Stop Control value

Note: Gating logic is outside of this macro
ValueDescription
0POSC clock source runs as normal
1POSC clock source is stopped