13.17.9 PBx Clock Divisor Control
Note: The system unlock sequence must be
done before this register can be written. PBx registers include PB1DIV, PB2DIV and
PB3DIV. Ensure the PB3DIV[6:0] value is equal to 0x09 or greater if the user is not
using Microchip-provided boot code.
| Name: | PBxDIV |
| Offset: | 0x0130 + (x-1)*0x10 [x=1..3] |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PB1DIVON | PB1DIVRDY | ||||||||
| Access | R | R | |||||||
| Reset | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PB1DIV[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
Bit 15 – PB1DIVON Output Enable bit
| Value | Description |
|---|---|
| 1 | PB1 Output clock is enabled |
| 0 | PB1
Output clock is disabled Note: PB1DIV[PB1DIVON] bit cannot be written to a ‘ 0’, as
this clock is used by the system CLK_RST
macro. |
Bit 11 – PB1DIVRDY PB1 Peripheral Clock Divisor Ready
| Value | Description |
|---|---|
| 1 | Indicates the PB clock divisor logic is not switching divisors and the PB1DIV may be written. |
| 0 | Indicates the PB clock divisor logic is currently switching values and the PB1DIV cannot be written. |
Bits 6:0 – PB1DIV[6:0] PB1 Peripheral Clock Divisor Control value
| Value | Description |
|---|---|
| 000_0000 | Divide by 1 PB1 Clock same frequency as SYS_CLK |
| 000_0001 | Divide by 2 PB1 Clock is 1/2 of SYS_CLK |
| 000_0010 | Divide by 3 PB1 Clock is 1/3 of SYS_CLK |
| 000_0011 | Divide by 4 PB1 Clock is 1/4 of SYS_CLK |
| ... | ... |
| ... | ... |
| 000_1111 | Divide by 16 PB1 Clock is 1/16 of SYS_CLK |
| 001_0000 | Divide by 17 PB1 Clock is 1/17 of SYS_CLK |
| ... | ... |
| ... | ... |
| 111_1110 | Divide by 127 PB1 Clock is 1/127 of SYS_CLK |
| 111_1111 | Divide by 128 PB1 Clock is 1/128 of SYS_CLK |