13.17.10 Slew Rate Control for Clock Switching

Note:

The system unlock sequence must be done before this register can be written.
Updates to this register do not take effect until OSCCON[OSWEN] is set.

Name:	SLEWCON
Offset:	0x160
Reset:	0x00000000


Bit	31	30	29	28	27	26	25	24
					SLW_DELAY[3:0]
Access					R/W	R/W	R/W	R/W
Reset					c	c	c	c


Bit	23	22	21	20	19	18	17	16
					SYS_DIV[3:0]
Access					R/W	R/W	R/W	R/W
Reset					c	c	c	c


Bit	15	14	13	12	11	10	9	8
						SLW_DIV[2:0]
Access						R/W	R/W	R/W
Reset						c	c	c


Bit	7	6	5	4	3	2	1	0
						SLW_UP	SLW_DN	SLW_BUSY
Access						R/W	R/W	R/W
Reset						c	c	c

Bits 27:24 – SLW_DELAY[3:0] Number of clocks generated at each slew step for a clock switch

Note: The reset value of this register field is defined by the input cfg_slewcon_sel[].

Value	Description
0000	1 clock will be generated at each slew step
0001	2 clocks will be generated at each slew step
...	...
1111	16 clocks will be generated at each slew step

Bits 19:16 – SYS_DIV[3:0] PBx Peripheral Clock Divisor Control value

Value	Description
0000	Divide by 1 – SYS_CLK_OUT same frequency as SYS_CLK source - Default
0001	Divide by 2 – SYS_CLK_OUT is 1/2 of SYS_CLK source
0010	Divide by 3 – SYS_CLK_OUT is 1/3 of SYS_CLK source
...	...
1111	Divide by 16 – SYS_CLK_OUT is 1/16 of SYS_CLK source

Bits 10:8 – SLW_DIV[2:0] Divisor steps used when doing slewed clock switches

Note: Each Divisor step lasts four clocks

Value	Description
000	No divisor is used
001	Divide by 2 (2¹), then no divisor
010	Divide by 4 (2²), then by 2, then no divisor
011	Divide by 8 (2³), then by 4, then by 2, then no divisor
100	Divide by 16 (2⁴), then by 8, then by 4, then by 2, then no divisor
...	...
111	Divide by 128 (2⁷), then by 64, then by 32, then by 16, then by 8, then by 4, then by 2, then no divisor

Bit 2 – SLW_UP Clock slew enable for switching up to faster clocks

Value	Description
0	Clock Slewing is disabled
1	Clock Slewing is enabled on a clock switch OR exit from Sleep

Bit 1 – SLW_DN Clock slew enable for switching down to slower clocks

Value	Description
0	Clock Slewing is disabled
1	Clock Slewing is enabled on a clock switch

Bit 0 – SLW_BUSY Clock Switch Slewing Active Status Bit – Read-Only

Value	Description
0	Clock Switch has reached its final value
1	Clock frequency is being actively Slewed

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