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PIC32CX-BZ2 and WBZ45 Family Data Sheet
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PIC32CX1012BZ24032
PIC32CX1012BZ25048
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WBZ451HUE
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WBZ451UE
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13
Clock and Reset Unit (CRU)
13.15
Resets
13.15.3
Modes of Operation
Introduction
PIC32CX-BZ2
SoC Family Features
WBZ45
Module Features
Acronyms and Abbreviations
1
Ordering Information
2
Configuration Summary
3
PIC32CX-BZ2
SoC Description
4
WBZ45
Module Description
5
Pinout and Signal Descriptions List
6
I/O Ports and Peripheral Pin Select (PPS)
7
Power Subsystem
8
Product Memory Mapping Overview
9
Prefetch Cache (PCHE)
10
Processor and Architecture
11
Cortex M Cache Controller (CMCC)
12
Device Service Unit (DSU)
13
Clock and Reset Unit (CRU)
13.1
Overview
13.2
Features
13.3
Block Diagram
13.4
System and Peripheral Clock Generation (CLKGEN)
13.5
Idle Mode
13.6
Dream Mode
13.7
FRCDIV
13.8
RFPLL Wrapper
13.9
Start-up Considerations
13.10
Fail-Safe Clock Monitor
13.11
Fast RC Oscillator
13.12
Secondary Oscillator
13.13
Low Power RC Oscillator (LPRC)
13.14
Reference Clock Generator
13.15
Resets
13.15.1
Control Registers
13.15.2
Reset Control Registers
13.15.3
Modes of Operation
13.15.3.1
System Reset (SYSRST)
13.15.3.2
Power-on Reset (POR)
13.15.3.3
Master Clear Reset
13.15.3.4
Software Reset (SWR)
13.15.3.5
Watchdog Timer Reset (WDTR)
13.15.3.6
Brown-out Reset (BOR)
13.15.3.7
Configuration Mismatch Reset (CMR)
13.15.3.8
Deadman Timer Reset (DMTR)
13.15.3.9
Non-maskable Interrupt (NMI) Timer
13.15.3.10
Determining the Source of Device Reset
13.15.4
Effects of Various Resets
13.15.5
CRU Configuration Registers
13.16
Register Summary
13.17
Register Description
14
RAM Error Correction Code (RAMECC)
15
Power Management Unit (PMU)
16
Watchdog Timer (WDT)
17
Deadman Timer (DMT)
18
System Configuration and Register Locking (CFG)
19
Register Locking
20
Peripheral Module Disable Register (PMD)
21
Real-Time Counter and Calendar (RTCC)
22
Direct Memory Access Controller (DMAC)
23
External Interrupt Controller (EIC)
24
Flash Memory
25
Integrity Check Monitor (ICM)
26
Peripheral Access Controller (PAC)
27
Frequency Meter (FREQM)
28
Event System (EVSYS)
29
Serial Communication Interface (SERCOM)
30
SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
31
SERCOM Serial Peripheral Interface (SERCOM SPI)
32
SERCOM Inter-Integrated Circuit (SERCOM I
2
C)
33
Quad Serial Peripheral Interface (QSPI)
34
Configurable Custom Logic (CCL)
35
True Random Number Generator (TRNG)
36
Advanced Encryption Standard (AES)
37
Public Key Cryptography Controller (PUKCC)
38
Analog-to-Digital Converter (ADC)
39
Analog Comparators (AC)
40
Timer/Counter (TC)
41
Timer/Counter for Control Applications (TCC)
42
Zigbee® Bluetooth® Radio Subsystem
43
Electrical Characteristics
44
Packaging Information
45
Appendix A: Regulatory Approval
46
Appendix B: Acronyms and Abbreviations
47
Document Revision History
Microchip Information
13.15.3 Modes of Operation
