3.4.3 SPI Settings

SPI settings include the following:

  • Clock speed
  • SPI mode
  • Chip-select selection and its active state
  • Delay between:
    • Chip-select assertion and to the first data byte
    • Between the data bytes
    • Last data byte and chip-select deassertion

These settings are shown in Table 3-6.

Table 3-6. I/O Pin Settings Map
Byte IndexRegister nameComments
0bSpeed

SPI clock frequency: 0x30 = 12 MHz; 0x20 = 6 MHz; 0x32 = 3 MHz; 0x22 = 1.5 MHz; 0x34 = 750 kHz; 0x24 = 375 kHz; 0x26 = 187.5 kHz

1bMode

SPI mode: 0x44 = Mode 0; 0x45 = Mode 1; 0x46 = Mode 2; 0x47 = Mode 3

2bChipSelect-ActiveState

Chip-select and its active state: 0x00 = CS0 active low; 0x01 = CS0 active high; 0x40 = CS1 active low; 0x41 = CS1 active high; 0x80 = CS2 active low; 0x81 = CS2 active high; 0xC0 = CS3 active low; 0xC1 = CS3 active high

3wDelay

Delay between chip-select assertion and the first data byte, between two data bytes, and between the last data byte and chip select deassertion:

For example: 0x0000 = 0μs; 0x000A = 10 μs; 0x0014 = 20 μs; 0x03E8 = 1000 μs; 0x1388 = 5000 μs