3.8 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 | Reserved | |||||||||
| 0x01 | DEVCFG | 7:0 | SLFPWR | RMTWKP | SNEN | |||||
| 0x02 | IO0SETTING | 7:0 | IDLST0 | ALRT0EG[1:0] | OD0SEL | PU0SEL | IO0DIR | IO0DES[1:0] | ||
| 0x03 | IO1SETTING | 7:0 | IDLST1 | OD1SEL | PU1SEL | IO1DIR | IO1DES[1:0] | |||
| 0x04 | IO2SETTING | 7:0 | IDLST2 | ALRT1EG[1:0] | OD2SEL | PU2SEL | IO2DIR | IO2DES[1:0] | ||
| 0x05 | IO3SETTING | 7:0 | IDLST3 | CLKDIV[1:0] | OD3SEL | PU3SEL | IO3DIR | IO3DES[1:0] | ||
| 0x06 | IO4SETTING | 7:0 | IDLST4 | ALRT2EG[1:0] | OD4SEL | PU4SEL | IO4DIR | IO4DES[1:0] | ||
| 0x07 | IO5SETTING | 7:0 | IDLST5 | ALRT3EG[1:0] | OD5SEL | PU5SEL | IO5DIR | IO5DES[1:0] | ||
| 0x08 | CFGPRTN | 7:0 | CFGPRO[1:0] | |||||||