Libero® SoC v2022.2

Introduction
1 About SmartTime
2 Design Flows with SmartTime
3 Starting and Closing SmartTime
4 Configuring SmartTime Settings
5 SmartTime Toolbar
6 SmartTime Timing Analyzer
7 Advanced Timing Analysis
8 Generating Timing Reports
- 8.1 Types of Reports
- 8.2 Generating a Timing Report
  The Timing Report allows you to determine whether timing problems exist in your design.
- 8.3 Understanding Timing Reports
- 8.4 Generating a Timing Violation Report
  The Timing Violations Report provides a Flat Slack Report centered around constraint violations.
- 8.5 Understanding Timing Violation Reports
- 8.6 Generating a Constraints Coverage Report
  The Constraints Coverage Report contains information about the constraints in the design.
- 8.7 Understanding Constraints Coverage Reports
- 8.8 Generating a Bottleneck Report
- 8.9 Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire
- 8.10 Generating a Datasheet Report
  The Datasheet Report shows information about a design’s external characteristics.
- 8.11 Understanding Datasheet Reports
- 8.12 Generating a Combinational Loop Report
  The Combinational Loop Report shows all loops found during initialization and reports pins associated with the loop(s) and the location where a loop is broken.
- 8.13 Understanding Combinational Loop Reports
- 8.14 Generating a Clock Domain Crossing (CDC) Report
  The Clock Domain Crossing (CDC) Report analyzes timing paths that cross from one clock domain (the source clock) to another clock domain (the destination clock). The CDC report helps identify instances where there may be data loss or metastability issues.
9 Timing Concepts
10 SmartTime Tutorials
11 SmartTime Dialog Boxes
12 Tcl Commands
13 Glossary
14 Revision History
Microchip FPGA Support
Microchip Information

8.11 Understanding Datasheet Reports

The Datasheet Report displays the external characteristics of the design. You can generate this report from SmartTime Max/Min Delay Analysis View.

Figure 8-5. Sample Datasheet Report

Table 8-6. Datasheet Report Tables
Table	Description
Pin Description	Provides the port name in the netlist, location on the package, type of port, and I/O technology assigned to it. Types can be input, output, or clock. Clock ports are ports shown as "clock" in the Clock domain browser.
DC Electrical Characteristics	Provides the parameters of the different I/O technologies used in the design. The number of parameters displayed depends on the family for which you have created the design.
AC Electrical Characteristics	Provides the timing properties of the ports of the design. For each clock, this section includes the maximum frequency. For each input, it includes the external setup, external hold, external recovery, and external removal for every clock where it applies. For each output, it includes the clock-to-out propagation time. This section also displays the input-to-output propagation time for combinational paths.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.