Libero® SoC v2022.2

Introduction
1 About SmartTime
2 Design Flows with SmartTime
3 Starting and Closing SmartTime
4 Configuring SmartTime Settings
5 SmartTime Toolbar
6 SmartTime Timing Analyzer
7 Advanced Timing Analysis
8 Generating Timing Reports
- 8.1 Types of Reports
- 8.2 Generating a Timing Report
  The Timing Report allows you to determine whether timing problems exist in your design.
- 8.3 Understanding Timing Reports
- 8.4 Generating a Timing Violation Report
  The Timing Violations Report provides a Flat Slack Report centered around constraint violations.
- 8.5 Understanding Timing Violation Reports
- 8.6 Generating a Constraints Coverage Report
  The Constraints Coverage Report contains information about the constraints in the design.
- 8.7 Understanding Constraints Coverage Reports
- 8.8 Generating a Bottleneck Report
- 8.9 Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire
- 8.10 Generating a Datasheet Report
  The Datasheet Report shows information about a design’s external characteristics.
- 8.11 Understanding Datasheet Reports
- 8.12 Generating a Combinational Loop Report
  The Combinational Loop Report shows all loops found during initialization and reports pins associated with the loop(s) and the location where a loop is broken.
- 8.13 Understanding Combinational Loop Reports
- 8.14 Generating a Clock Domain Crossing (CDC) Report
  The Clock Domain Crossing (CDC) Report analyzes timing paths that cross from one clock domain (the source clock) to another clock domain (the destination clock). The CDC report helps identify instances where there may be data loss or metastability issues.
9 Timing Concepts
10 SmartTime Tutorials
11 SmartTime Dialog Boxes
12 Tcl Commands
13 Glossary
14 Revision History
Microchip FPGA Support
Microchip Information

8.7 Understanding Constraints Coverage Reports

The Constraints Coverage Report shows the overall coverage of the timing constraints set on the current design. You can generate this report either from within Designer or within SmartTime Analyzer.

Figure 8-3. Sample Constraints Coverage Report

Table 8-4. Constraints Coverage Report Sections
Section	Description
Coverage Summary	Shows statistical information about the timing constraint in the design. For each type of timing checks (Setup, Recovery, Output, Hold, and Removal), it specifies how many are Met (there is a constraint and it is satisfied), Violated (there is a constraint and it is not satisfied), or Untested (no constraint was found).
Results by Clock Domain	This section provides a coverage summary for each clock domain.
Enhancement Suggestions	Reports, per clock domain, a list of constraints that can be added to the design to improve the coverage. It also reports if some options impacting the coverage can be changed.
Detailed Stats	Provides detailed suggestions about specific clocks or I/O ports that may require to be constrained for every pin/port that requires checks.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.