Libero® SoC v2022.2

Introduction
1 About SmartTime
2 Design Flows with SmartTime
3 Starting and Closing SmartTime
4 Configuring SmartTime Settings
5 SmartTime Toolbar
6 SmartTime Timing Analyzer
7 Advanced Timing Analysis
8 Generating Timing Reports
- 8.1 Types of Reports
- 8.2 Generating a Timing Report
  The Timing Report allows you to determine whether timing problems exist in your design.
- 8.3 Understanding Timing Reports
- 8.4 Generating a Timing Violation Report
  The Timing Violations Report provides a Flat Slack Report centered around constraint violations.
- 8.5 Understanding Timing Violation Reports
- 8.6 Generating a Constraints Coverage Report
  The Constraints Coverage Report contains information about the constraints in the design.
- 8.7 Understanding Constraints Coverage Reports
- 8.8 Generating a Bottleneck Report
- 8.9 Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire
- 8.10 Generating a Datasheet Report
  The Datasheet Report shows information about a design’s external characteristics.
- 8.11 Understanding Datasheet Reports
- 8.12 Generating a Combinational Loop Report
  The Combinational Loop Report shows all loops found during initialization and reports pins associated with the loop(s) and the location where a loop is broken.
- 8.13 Understanding Combinational Loop Reports
- 8.14 Generating a Clock Domain Crossing (CDC) Report
  The Clock Domain Crossing (CDC) Report analyzes timing paths that cross from one clock domain (the source clock) to another clock domain (the destination clock). The CDC report helps identify instances where there may be data loss or metastability issues.
9 Timing Concepts
10 SmartTime Tutorials
11 SmartTime Dialog Boxes
12 Tcl Commands
13 Glossary
14 Revision History
Microchip FPGA Support
Microchip Information

8.9 Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire

A bottleneck is a point in the design that contributes to multiple timing violations. The Bottleneck Report lists the bottlenecks in the design. You can generate this report from SmartTime Analyzer.

Note: The bottleneck can be computed only when a cost type is defined. There are two cost type options available:

Path count: associates the severity of the bottleneck to the count of violating/critical paths that traverse the instance.
Path cost: associates the severity of the bottleneck to the sum of the timing violations for the violating/critical paths that traverse the instance.

Figure 8-4. Sample Bottleneck Report

The Bottleneck Report contains the following parts:

Table 8-5. Bottleneck Report Sections
Part	Description
Device Description	Contains general information about the design, including: Design name Family Die Package Software version
Bottleneck Analysis	Lists the core of the bottleneck information. It is organized into two columns: Instance Name: refers to the output pin name of the instance. Path Count: shows the number of violating paths that include the instance pin.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.