37.5.2.1 Selection of Positive Inputs

For dedicated ADC core, one alternate selection is provided for each positive input. This alternate input can be chosen using the SH0ALT[1:0] bits in the ADC Triggering Mode Register (ADCTRGMODE) as follows:

• SH0ALT[1:0] (ADCTRGMODE[17:16])

For the shared ADC core, the positive input is shared among all Class 2 and Class 3 inputs. Input connection of the analog input ANx to the shared ADC is automatic for either the Class 2 input trigger or during a scan of Class 2 and or Class 3 inputs. Selecting inputs for scanning is described in Selecting the Scanned Inputs from Related Links.