2.3.7.1.1 Timing Characteristics

Table 2-76. Input DDR Propagation Delays Worst Military-Case Conditions: T_J = 85 °C, Worst Case VCC = 1.425V
Parameter	Description	–1	Std.	Units
t_DDRICLKQ1	Clock-to-Out Out_QR for Input DDR	0.41	0.49	ns
t_DDRICLKQ2	Clock-to-Out Out_QF for Input DDR	0.29	0.35	ns
t_DDRISUD	Data Setup for Input DDR	0.30	0.36	ns
t_DDRIHD	Data Hold for Input DDR	0.00	0.00	ns
t_DDRICLR2Q1	Asynchronous Clear-to-Out Out_QR for Input DDR	0.60	0.72	ns
t_DDRICLR2Q2	Asynchronous Clear-to-Out Out_QF for Input DDR	0.49	0.59	ns
t_DDRIREMCLR	Asynchronous Clear Removal time for Input DDR	0.00	0.00	ns
t_DDRIRECCLR	Asynchronous Clear Recovery time for Input DDR	0.24	0.28	ns
t_DDRIWCLR	Asynchronous Clear Minimum Pulse Width for Input DDR	0.22	0.26	ns
t_DDRICKMPWH	Clock Minimum Pulse Width High for Input DDR	0.36	0.42	ns
t_DDRICKMPWL	Clock Minimum Pulse Width Low for Input DDR	0.32	0.38	ns
F_DDRIMAX	Maximum Frequency for Input DDR	350	350	MHz

Note: For derating values at specific junction temperature and voltage-supply levels, refer to Table 2-7 for derating values.