2.2.2 Power per I/O Pin

Table 2-10. Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
VCCFPGAIOBx (V)Static Power
PDC7 (mW)Dynamic Power PAC9 (µW/MHz)
Single-Ended
3.3V LVTTL/3.3V LVCMOS3.317.55
2.5V LVCMOS2.55.97
1.8V LVCMOS1.82.88
1.5V LVCMOS (JESD8-11)1.52.33
3.3V PCI3.319.21
3.3V PCI-X3.319.21
Differential
LVDS2.52.250.82
LVPECL3.35.741.16
Table 2-11. Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to MSS I/O Banks
VCCMSSIOBx (V)Static Power
PDC7 (mW)Dynamic Power
PAC9 (µW/MHz)
Single-Ended
3.3V LVTTL / 3.3V LVCMOS3.317.21
3.3V LVCMOS/3.3V LVCMOS – Schmitt trigger3.320.00
2.5V LVCMOS2.55.55
2.5V LVCMOS – Schmitt trigger2.57.03
1.8V LVCMOS1.82.61
1.8V LVCMOS – Schmitt trigger1.82.72
1.5V LVCMOS (JESD8-11)1.51.98
1.5V LVCMOS (JESD8-11) – Schmitt trigger1.51.93
Table 2-12. Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
CLOAD (pF)VCCFPGAIOBx (V)Static Power

PDC8 (mW)

Dynamic Power

PAC10 (µW/MHz)

Single-Ended
3.3V LVTTL / 3.3V LVCMOS353.3475.66
2.5V LVCMOS352.5270.50
1.8V LVCMOS351.8152.17
1.5V LVCMOS (JESD8-11)351.5104.44
3.3V PCI103.3202.69
3.3V PCI-X103.3202.69
Differential
LVDS2.57.7588.26
LVPECL3.319.54164.99
Note:
  1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
Table 2-13. Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to MSS I/O Banks
CLOAD (pF)VCCMSSIOBx (V)Static Power

PDC8 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended
3.3V LVTTL/3.3V LVCMOS103.319.67
2.5V LVCMOS102.511.23
1.8V LVCMOS101.85.82
1.5V LVCMOS (JESD8-11)101.54.07