2.2.4 Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

• The number of PLLs/CCCs as well as the number and the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• The number of eNVM blocks used in the design
• The analog block used in the design, including the temperature monitor, current monitor, ABPS, sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal oscillator
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-17.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-18.
• Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-18.
• Read rate to the eNVM blocks

The calculation should be repeated for each clock domain defined in the design.