49.7.4 TC Stepper Motor Mode Register n
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
| Name: | TC_SMMRn |
| Offset: | 0x08 + n*0x40 [n=0..2] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DOWN | GCEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DOWN Down Count
| Value | Description |
|---|---|
| 0 | Up counter. |
| 1 | Down counter. |
Bit 0 – GCEN Gray Count Enable
| Value | Description |
|---|---|
| 0 | TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x. |
| 1 | TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit Gray counter. |