36.8.112 GMAC Interrupt Mask Register Priority Queue n
Note:
- A read of this register returns the value of the receive complete interrupt mask.
- A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a '1' is written.
The following values are valid for all listed bit names of this register:
| Value | Description |
|---|---|
| 0 | Corresponding interrupt is enabled. |
| 1 | Corresponding interrupt is disabled. |
| Name: | GMAC_IMRPQn |
| Offset: | 0x0640 + n*0x04 [n=0..4] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HRESP | ROVR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | AHB | RLEX | RXUBR | RCOMP | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |