33.1.4 Conversion Clock

The conversion clock source is software selected with the ADCS bit. When ADCS = 1 the ADC clock source is an internal fixed-frequency clock referred to as FRC. When ADCS = 0 the ADC clock frequencies are derived from FOSC. The ADCLK33.7.6 ADCLK register selects one of 64 possible clock options from FOSC/2 to FOSC/128:

  • FOSC/2
  • FOSC/4
  • FOSC/6
  • FOSC/8
  • FOSC/10
  • ...
  • FOSC/128

The time to complete one bit conversion is defined as the TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 33-2.

For correct conversion, the appropriate TAD specification must be met. Refer to the "ADC Timing Specifications" for more information. The "ADC Clock Period" table below gives examples of appropriate ADC clock selections.

Important:
  1. Except for the FRC clock source, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
  2. The internal control logic of the ADC runs off of the clock selected by ADCS. When the ADCS is set to ‘1’ (ADC runs on FRC), there may be unexpected delays in operation when setting ADC control bits.
Table 33-2. ADC Clock Period (TAD) Vs. Device Operating Frequencies(1,4)
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
Clock Source ADCLK 64 MHz 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000000 31.25 ns(2) 62.5 ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 μs
FOSC/4 000001 62.5 ns(2) 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 μs 4.0 μs
FOSC/6 000010 125 ns(2) 187.5 ns(2) 300 ns(2) 375 ns(2) 750 ns(2) 1.5 μs 6.0 μs
FOSC/8 000011 187.5 ns(2) 250 ns(2) 400 ns(2) 500 ns(2) 1.0 μs 2.0 μs 8.0 μs(3)
... ... ... ... ... ... ... ... ...
FOSC/16 000111 250 ns(2) 500 ns(2) 800 ns(2) 1.0 μs 2.0 μs 4.0 μs 16.0 μs(3)
... ... ... ... ... ... ... ... ...
FOSC/128 111111 2.0 μs 4.0 μs 6.4 μs 8.0 μs 16.0 μs(3) 32.0 μs(2) 128.0 μs(2)
FRC ADCS=1 1.0-6.0 μs 1.0-6.0 μs 1.0-6.0 μs 1.0-6.0 μs 1.0-6.0 μs 1.0-6.0 μs 1.0-6.0 μs
Note:
  1. See TAD parameter in the "Electrical Specifications" section for FRC source typical TAD value.
  2. These values violate the required TAD time.
  3. Outside the recommended TAD time.
  4. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode.
Figure 33-2. Analog-to-Digital Conversion TAD Cycles