28.5.2.1 7-bit Addressing Reception
This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 28-14 and Figure 28-15 are used as a visual reference for this description.
This is a step by step process of what typically must be done to accomplish I2C communication.
- Start bit detected.
- S bit is set; SSPxIF is set if interrupt on Start detect is enabled.
- Matching address with R/W bit clear is received.
- The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit.
- Software clears the SSPxIF bit.
- Software reads received address from SSPxBUF clearing the BF flag.
- If SEN =
1
; Slave software sets CKP bit to release the SCL line. - The master clocks out a data byte.
- Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit.
- Software clears SSPxIF.
- Software reads the received byte from SSPxBUF clearing BF.
- Steps 8-12 are repeated for all received bytes from the master.
- Master sends Stop condition, setting P bit, and the bus goes Idle.