Jump to main content
High-Performance dsPIC33A Core with Floating-Point Unit, High Resolution PWM, High-Speed ADCs, CAN FD, I3C, Resolver Interface, Security Features
High-Performance dsPIC33A Core with Floating-Point Unit, High Resolution PWM, High-Speed ADCs, CAN FD, I3C, Resolver Interface, Security Features
  1. Home
  2. 14 CAN Flexible Data-Rate (FD) Protocol Module
  3. 14.7 Message Transmission
Previous | Next
  • Operating Conditions
  • High-Performance DSP CPU
  • Memory Features
  • Security Features
  • High-Resolution PWM
  • High-Speed Analog-to-Digital Converters
  • Peripheral Features
  • Controller Features
  • Analog Features
  • Safety Features
  • Functional Safety
  • Qualification
  • Programming and Debug Interfaces
  • dsPIC33AK256MPS306 Family Features
  • Pin Diagrams
  • Pinout I/O Descriptions
  • To Our Valued Customers
  • Terminology Cross Reference
  • 1 Device Overview
  • 2 Guidelines for Getting Started with Digital Signal Controllers
  • 3 CPU
  • 4 Memory Organization
  • 5 Data Memory
  • 6 Flash Program Memory
  • 7 Configuration Bits
  • 8 Security Module
  • 9 Resets
  • 10 Interrupt Controller
  • 11 I/O Ports with Edge Detect
  • 12 Oscillator and Clocking Module
  • 13 Direct Memory Access (DMA) Controller
  • 14 CAN Flexible Data-Rate (FD) Protocol Module
    • 14.1 Device-Specific Information
    • 14.2 Features
    • 14.3 CAN FD Message Frames
    • 14.4 Register Summary
    • 14.5 Modes of Operation
    • 14.6 Configuration
    • 14.7 Message Transmission
      • 14.7.1 Transmit Message Object
      • 14.7.2 Loading Messages into Transmit FIFO
      • 14.7.3 Loading Messages Into Transmit Queue
      • 14.7.4 Requesting Transmission of Message in Transmit FIFO
      • 14.7.5 Requesting Transmission of Message in Transmit Queue
      • 14.7.6 CxTXREQ Register
      • 14.7.7 Transmit Priority
      • 14.7.8 Transmit Bandwidth Sharing
      • 14.7.9 Retransmission Attempts
      • 14.7.10 Aborting Transmission
      • 14.7.11 Remote Transmit Request – RTR
      • 14.7.12 Mismatch of DLC and Payload Size During Transmission
      • 14.7.13 Transmit State Diagram
      • 14.7.14 Resetting Transmit FIFO
      • 14.7.15 Resetting Transmit Queue
      • 14.7.16 Message Transmission Code Example
    • 14.8 Transmit Event FIFO - TEF
    • 14.9 Message Filtering
    • 14.10 Message Reception
    • 14.11 FIFO Behavior
    • 14.12 Timestamping
    • 14.13 Interrupts
    • 14.14 Error Handling
  • 15 High-Resolution PWM with Fine-Edge Placement
  • 16 40 MSPS Analog-to-Digital Converter (ADC)
  • 17 Integrated Touch Controller (ITC)
  • 18 Resolver-to-Digital Converter (RDC)
  • 19 High-Speed Analog Comparator with Slope Compensation DAC
  • 20 Quadrature Encoder Interface (QEI)
  • 21 Universal Asynchronous Receiver Transmitter (UART)
  • 22 Serial Peripheral Interface (SPI)
  • 23 Inter-Integrated Circuit (I2C)
  • 24 Improved Inter-Integrated Circuit (I3C)
  • 25 Single-Edge Nibble Transmission (SENT)
  • 26 Bidirectional Serial Synchronous (BiSS) Module
  • 27 Timers
  • 28 Capture/Compare/PWM/Timer Modules (SCCP/MCCP)
  • 29 Configurable Logic Cell (CLC)
  • 30 Peripheral Trigger Generator (PTG)
  • 31 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
  • 32 Current Bias Generator (CBG)
  • 33 UREF Reference Output
  • 34 Operational Amplifier (Op Amp)
  • 35 Watchdog Timer (WDT)
  • 36 Deadman Timer (DMT)
  • 37 Device Power-Saving Modes
  • 38 JTAG Interface
  • 39 In-Circuit Debugger
  • 40 Instruction Set Summary
  • 41 Development Support
  • 42 Electrical Characteristics
  • 43 Packaging Information
  • 44 Revision History
  • 45 Product Identification System
  • Microchip Information

14.7 Message Transmission

The application has to configure the FIFO or TXQ before it can be used for transmission (see Transmit FIFO Configuration and Transmit Queue Configuration).

DS70005629B

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

About
Company
Careers
Contact Us
Media Center
Investor Relations
Corporate Responsibility

Support
Microchip Forums
AVR Freaks
Design Help
Technical Support
Export Control Data
PCNs

Quick Links
microchipDIRECT.com
Microchip University
myMicrochip
Blogs
Reference Designs
Parametric Search
Microchip Logo

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, Arizona, USA

Microchip Facebook
Microchip LinkedIn
Microchip Twitter
Microchip Instagram
Microchip Weibo

© Copyright 1998-2024 Microchip Technology Inc. All rights reserved. Shanghai ICP Recordal No.09049794

Terms Of Use
Privacy Notice
Legal
Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon