22.3.7 SPIx Underrun Data Register

Legend: R = Readable bit; W = Writable bit

Name: SPIxURDT
Offset: 0x1818 + (x-1)*0x04 [x=1..3]

Bit 3130292827262524 
 SPIxURDT[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 SPIxURDT[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 SPIxURDT[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 SPIxURDT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – SPIxURDT[31:0] SPI Underrun Data bits

These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit Underrun condition occurs.

Table 22-6 summarizes the valid data fields for possible values of the MODE32, MODE16 and WLENGTH[4:0] bits.
Table 22-6. MODE32, MODE16 and WLENGTH[4:0] Data Fields
MODE32MODE16WLENGTH[4:0]COMMUNICATIONValid Data Field
1X032-bitDATA[31:0]
01016-bitDATA[15:0]
0008-bitDATA[07:0]
XX16 < N < 31(N+1)-bitDATA[31:(31-N)]
XX8 < N < 15(N+1)-bitDATA[15:(15-N)]
XX1 < N < 7(N+1)-bitDATA[07:(07-N)]