22.3.1 SPIx Control Register 1

Audio protocol is enabled; MSTEN controls the direction of both SCKx and frame (a.k.a. LRC), and this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and SMP = 0, regardless of their actual values.

Audio protocol is disabled. When AUDEN = 0, TDM mode is supported using SPI Frame Mode and DMA channels.

Data from RX FIFO is sign-extended (upper unused bits should replicate the MSb of the received data).

Data from RX FIFO is not sign-extended (upper unused bits are always 1'b0).

A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO is not overwritten by the received data.

An ROV is a critical error that stops SPI operation.

A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN is transmitted until the SPIxTXB is not empty.

A TUR is a critical error that stops SPI operation.

Audio data is mono (i.e., each data word is transmitted on both the left and right channels).

Audio data is stereo.

Transmits data out of the SPIxURDT register during Transmit Underrun conditions.

Transmits the last received data during Transmit Underrun conditions.

PCM/DSP mode

Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value.

Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value.

I²S mode: This module functions as if SPIFE = 0, regardless of its actual value.

Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output).

Framed SPIx support is disabled.

Frame Sync pulse input (client)

Frame Sync pulse output (host)

Frame Sync pulse/Client Select is active high.

Frame Sync pulse/Client Select is active low.

SPIx Client Select support is enabled with polarity determined by FRMPOL (SSx pin is automatically driven during transmission in Host mode).

Client Select SPIx support is disabled (SSx pin will be controlled by port I/O).

Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0]).

Frame Sync pulse is one clock (SCKx) wide.

Reserved

Reserved

Generate/Receive a Frame Sync pulse every 32 serial words.

Generate/Receive a Frame Sync pulse every 16 serial words.

Generate/Receive a Frame Sync pulse every 8 serial words.

Generate/Receive a Frame Sync pulse every 4 serial words.

Generate/Receive a Frame Sync pulse every 2 serial words (value used by audio protocols).

Generate/Receive a Frame Sync pulse each serial word.

Enables module.

Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications.

Halts in CPU Idle mode.

Continues to operate in CPU Idle mode.

SDOx pin is not used by the module; pin is controlled by port function.

SDOx pin is controlled by the module.

Input data is sampled at the end of data output time.

Input data is sampled at the middle of data output. time

Transmit happens on the transition from the active clock state to the Idle clock state.

Transmit happens on the transition from the Idle clock state to the active clock state.

SSx pin is used by the module in Client mode; the SSx pin is used as the Client Select input.

SSx pin is not used by the module (the pin is controlled by the port function).

Idle state for the clock is a high level; the active state is a low level.

Idle state for the clock is a low level; the active state is a high level.

Host mode

Client mode

SDIx pin is not used by the module; the pin is controlled by the port function.

SDIx pin is controlled by the module.

SCKx pin is not used by the module; the pin is controlled by the port function.

SCKx pin is controlled by the module.

Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock.

Frame Sync pulse (Idle-to-active edge) precedes the first bit clock.

Enhanced Buffer mode is enabled.

Enhanced Buffer mode is disabled.