9.2.9.1 Device Reset to Code Execution Start Time

The delay between the end of a Reset event and when the device actually begins to execute code is determined by two main factors: the type of Reset and the system clock source coming out of the Reset. The code execution start time for various types of device Resets is summarized in Table 9-2. Individual delays are characterized in the Electrical Characteristics section.

Table 9-2. Code Execution Start Time for Various Device Resets
Reset TypeClock SourcePower-Up Delay(1,2,3)System Clock
Delay(4,5)FSCM Delay(6)
POREC, FRC, FRCDIV, LPRC(Tpu or Tpwrt) + Tsysdly——
ECPLL, FRCPLL(Tpu or Tpwrt) + TsysdlyTlockTfscm
XT(Tpu or Tpwrt) + TsysdlyTostTfscm
XTPLL, HSPLL(Tpu or Tpwrt) + TsysdlyTost + TlockTfscm
BOREC, FRC, FRCDIV, LPRCTsysdly——
ECPLL, FRCPLLTsysdlyTlockTfscm
XTTsysdlyTostTfscm
XTPLLTsysdlyTost + TlockTfscm
MCLR, CMR, SWR, WDTO, DMTO, PWRMRAny ClockTsysdly——
For parameter specifications, see the Electrical Characteristics chapter.
  1. Tpu = Power-up Period with on-chip regulator enabled
  2. Tpwrt = Power-up Period (Power-up Timer) with on-chip regulator disabled
  3. Tsysdly = Time required to reload Device Configuration Fuses plus eight SYSCLK cycles
  4. Tost = Oscillator Start-up Timer
  5. Tlock = PLL lock time
  6. Tfscm = Fail-Safe Clock Monitor delay