10.4.33 Interrupt Priority Register 2

Name: IPC2
Offset: 0xF8

Bit 3130292827262524 
  CM4FAILIP[2:0] CM3CNTIP[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100100 
Bit 2322212019181716 
  CM3SATIP[2:0] CM3WARNIP[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100100 
Bit 15141312111098 
  CM3FAILIP[2:0] CM2CNTIP[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100100 
Bit 76543210 
  CM2SATIP[2:0] CM2WARNIP[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100100 

Bits 30:28 – CM4FAILIP[2:0] Clock Monitor 4 Clock Failure Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 26:24 – CM3CNTIP[2:0] Clock Monitor 3 Count Ready Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 22:20 – CM3SATIP[2:0] Clock Monitor 3 Saturation Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 18:16 – CM3WARNIP[2:0] Clock Monitor 3 Clock Warning Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 14:12 – CM3FAILIP[2:0] Clock Monitor 3 Clock Failure Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 10:8 – CM2CNTIP[2:0] Clock Monitor 2 Count Ready Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 6:4 – CM2SATIP[2:0] Clock Monitor 2 Saturation Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 2:0 – CM2WARNIP[2:0] Clock Monitor 2 Clock Warning Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)