42.4.1 External Clock/Oscillator Timing Requirements

Figure 42-4. Clock Timing

Table 42-7.
Standard Operating Conditions (unless otherwise stated)
Param No.	Sym.	Characteristic	Min.	Typ. †	Max.	Units	Conditions
ECL Oscillator
OS1	F_ECL	Clock Frequency	—	—	1	MHz
OS2	T_{ECL_DC}	Clock Duty Cycle	40	—	60	%
ECH Oscillator
OS5	F_ECH	Clock Frequency	—	—	32	MHz
OS6	T_{ECH_DC}	Clock Duty Cycle	40	—	60	%
LP Oscillator
OS7	F_LP	Clock Frequency	—	32	100	kHz	⁽³⁾
XT Oscillator
OS8	F_XT	Clock Frequency	—	—	4	MHz	⁽³⁾
HS Oscillator
OS9	F_HS	Clock Frequency	—	—	20	MHz	⁽³⁾
Secondary Oscillator
OS13*	F_SEC	Clock Frequency	32.4	32.768	33.1	kHz
OS14*	C_OSC1/OSC2	Parasitic Pin Capacitance	—	5	—	pF
OS15*	C_L	Crystal Load Capacitance	—	—	8	pF	SOSCPWR = `0`
OS15A*	C_L	Crystal Load Capacitance	—	—	18	pF	SOSCPWR = `1`
OS16*	R_ES	Equivalent Series Resistance	—	—	50	Ω	SOSCPWR = `0`
OS16A*	R_ES	Equivalent Series Resistance	—	—	100	Ω	SOSCPWR = `1`
System Oscillator
OS20	F_OSC	System Clock Frequency	—	—	32	MHz	⁽²⁾
OS21	F_CY	Instruction Frequency	—	F_OSC/4	—	MHz
OS22	T_CY	Instruction Period	125	1/F_CY	—	ns
Note: Instruction cycle period (T_CY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. The system clock frequency (F_OSC) is selected by the “main clock switch controls” as described in the “Power-Saving Mode Operation” section. The LP, XT, and HS Oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used.