4.1.4 Mi-V Subsystem

The Mi_V_Subsystem SmartDesign operates at 100 MHz. It implements an AHB interface and GPIO interface. The following figure shows how the AHB interface is used to access the CPRI configuration registers, and the GPIO interface is used to indicate configuration status.

Figure 4-9. Mi-V Subsystem

For more information about how to build the Mi-V subsystem, see TU0775 Tutorial PolarFire FPGA: Building a Mi-V Processor Subsystem .

The following table lists the address map of Mi-V processor.

Table 4-1. System Memory Map
ComponentMemory MapDescription
CoreGPIO0x60051000This bus interface is used to access the GPIO's through APB interface.
CPRI Slave IP0x60060000This bus interface is used to access CPRI slave IP configuration registers through the AHB interface.
CPRI Master module0x60070000This bus interface is used to access CPRI master configuration registers through the AHB interface.