4.1.3 Transceiver Subsystem

The transceiver is configured for the following characteristics:

  • Two lanes at 122.88 MHz clock, each lane carries 32-bit IQ data
  • 32-bit PCS interface
  • Data rate of 4.9152 Gbps
  • Lane 0 is configured for Master and Lane 1 is configured for Slave
Figure 4-8. Transceiver Subsystem