23.5.2 Channel n Generator Selection
Each event channel can be connected to a single event generator.
Refer to the Peripheral Overview section for the available Event System channels.
| Name: | CHANNELn |
| Offset: | 0x10 + n*0x01 [n=0..5] |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHANNEL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – CHANNEL[7:0] Channel Generator Selection
Note: Not all generators can be connected to all channels. Refer
to the table below for further details.
Note:
- Not all peripheral instances are available for all pin counts. Refer to the Peripherals and Architecture section for details.
- An event from the PORT pin will be zero if the input driver is disabled.
- The operational mode of the timer decides when the CAPT flag is raised. Refer to the TCB section for details.
| Value | Name | Description |
|---|---|---|
| 0x00 | OFF | This Event System Channel is disabled. |
| 0x01 | UPDI_SYNCH | The rising edge of SYNCH character detection. An asynchronous event, available on all channels. |
| 0x03 | WDT_TICK | WDT LSB Tick. An asynchronous event. Available on all channels. |
| 0x04 | SWDT_ERROR | SWDT ERROR. A synchronous event. Available on all channels. |
| 0x05 | MVIO_VDDIO2OK | VDDIO2 OK. An asynchronous event. Available on all channels. |
| 0x06 | RTC_OVF | Counter overflow. An asynchronous event. Available on all channels. |
| 0x07 | RTC_CMP | Compare match. An asynchronous event. Available on all channels. |
| 0x08 | RTC_EVGEN0 | Selectable prescaled RTC event. An asynchronous event. Available on all channels. |
| 0x09 | RTC_EVGEN1 | Selectable prescaled RTC event. An asynchronous event. Available on all channels. |
| 0x10 | CCL_LUT0 | LUT output level. An asynchronous event. Available on all channels. |
| 0x11 | CCL_LUT1 | LUT output level. An asynchronous event. Available on all channels. |
| 0x12 | CCL_LUT2 | LUT output level. An asynchronous event. Available on all channels. |
| 0x13 | CCL_LUT3 | LUT output level. An asynchronous event. Available on all channels. |
| 0x14 | CCL_LUT4 | LUT output level. An asynchronous event. Available on all channels. |
| 0x15 | CCL_LUT5 | LUT output level. An asynchronous event. Available on all channels. |
| 0x20 | AC0_OUT | Comparator output level. An asynchronous event. Available on all channels. |
| 0x21 | AC1_OUT | Comparator output level. An asynchronous event. Available on all channels. |
| 0x22 | AC2_OUT | Comparator output level. An asynchronous event. Available on all channels. |
| 0x24 | ADC0_RESRDY | Result ready. A synchronous event. Available on all channels. |
| 0x25 | ADC0_SAMPRDY | Sample ready. A synchronous event. Available on all channels. |
| 0x26 | ADC0_WCMP | Window comparison match. A synchronous event. Available on all channels. |
| 0x27 | ADC1_RESRDY | Result ready. A synchronous event. Available on all channels. |
| 0x28 | ADC1_SAMPRDY | Sample ready. A synchronous event. Available on all channels. |
| 0x29 | ADC1_WCMP | Window comparison match. A synchronous event. Available on all channels. |
| 0x30 | ZCD0_OUT | Given by ZCD output level. An asynchronous event. Available on all channels. |
| 0x33 | ZCD3_OUT | Given by ZCD output level. An asynchronous event. Available on all channels. |
| 0x40 | PORTA_EVGEN0 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x41 | PORTA_EVGEN1 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x42 | PORTB_EVGEN0(1) | Pin level(2). An asynchronous event. Available on all channels. |
| 0x43 | PORTB_EVGEN1(1) | Pin level(2). An asynchronous event. Available on all channels. |
| 0x44 | PORTC_EVGEN0 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x45 | PORTC_EVGEN1 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x46 | PORTD_EVGEN0 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x47 | PORTD_EVGEN1 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x48 | PORTE_EVGEN0 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x49 | PORTE_EVGEN1 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x4A | PORTF_EVGEN0 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x4B | PORTF_EVGEN1 | Pin level(2). An asynchronous event. Available on all channels. |
| 0x60 | USART0_XCK | Clock signal in SPI Host mode and synchronous USART Host mode. A synchronous event, available on all channels. |
| 0x61 | USART1_XCK | Clock signal in SPI Host mode and synchronous USART Host mode. A synchronous event. Available on all channels. |
| 0x62 | USART2_XCK(1) | Clock signal in SPI Host mode and synchronous USART Host mode. A synchronous event. Available on all channels. |
| 0x68 | SPI0_SCK | SPI Host clock signal. A synchronous event. Available on all channels. |
| 0x69 | SPI1_SCK | SPI Host clock signal. A synchronous event. Available on all channels. |
| 0x80 | TCA0_OVF_LUNF | Overflow/Low-byte timer underflow. A synchronous event. Available on all channels. |
| 0x81 | TCA0_HUNF | High byte timer underflow. A synchronous event. Available on all channels. |
| 0x84 | TCA0_CMP0_LCMP0 | Compare channel 0 match/Low-byte timer compare channel 0 match. A synchronous event. Available on all channels. |
| 0x85 | TCA0_CMP1_LCMP1 | Compare channel 1 match/Low-byte timer compare channel 1 match. A synchronous event. Available on all channels. |
| 0x86 | TCA0_CMP2_LCMP2 | Compare channel 2 match/Low-byte timer compare channel 2 match. A synchronous event. Available on all channels. |
| 0xA0 | TCB0_CAPT | CAPT Interrupt flag set(3). A synchronous event. Available on all channels. |
| 0xA1 | TCB0_OVF | Counter overflow. A synchronous event. Available on all channels. |
| 0xA2 | TCB1_CAPT | CAPT Interrupt flag set(3). A synchronous event. Available on all channels. |
| 0xA3 | TCB1_OVF | Counter overflow. A synchronous event. Available on all channels. |
| 0xA4 | TCB2_CAPT | CAPT Interrupt flag set(3). A synchronous event. Available on all channels. |
| 0xA5 | TCB2_OVF | Counter overflow. A synchronous event. Available on all channels. |
| 0xA6 | TCB3_CAPT | CAPT Interrupt flag set(3). A synchronous event. Available on all channels. |
| 0xA7 | TCB3_OVF | Counter overflow. A synchronous event. Available on all channels. |
| 0xB0 | TCD0_CMPBCLR | Counter matches CMPBCLR. A synchronous event. Available on all channels. |
| 0xB1 | TCD0_CMPASET | Counter matches CMPASET. A synchronous event. Available on all channels. |
| 0xB2 | TCD0_CMPBSET | Counter matches CMPBSET. A synchronous event. Available on all channels. |
| 0xB3 | TCD0_PROGEV | Programmable event output. An asynchronous event. Available on all channels. |