38.3.2.4 Error Injection
The CRCSCAN error injection triggers a rapid CRC scan, resulting in a CRC error.
Writing a ‘1
’ to the Inject CRC Error (EINJ) bit in the Control B
(CRCSCAN.CTRLB) register will trigger a scan that starts when the CPU enters Idle sleep
mode.
No error injection will be performed if the BUSY bit in the Status A (CRCSCAN.STATUSA)
register is ‘1
’ or if CRCSCAN is in the Manual mode (determined by the CRC
Source (SRC) bit field in the Control A (CRCSCAN.CTRLA) register).
The error-injected scan is performed by only scanning the last four words in the section
selected by the SRC bit in the CRCSCAN.CTRLA register and comparing the CRC with the
pre-calculated checksum described in the Checksum section. As the checksums will
differ, the ERROR bit in the CRCSCAN.STATUSA register will be set to ‘1
’
at the end of the scan.
The status flags in the Interrupt Flags (CRCSCAN.INTFLAGS) register are updated (as after
an ordinary scan), and an interrupt is generated if the DONE bit in the Interrupt Control
(CRCSCAN.INTCTRL) register is set. Error injection when the Enable NMI Trigger (NMIEN) bit
in the CRCSCAN.CTRLA register is ‘1
’ will trigger an NMI request.
Error injection does not start in sleep unless the Enable CRCSCAN (ENABLE) bit in the
CRCSCAN.CTRLA register is ‘1
’. Writing a ‘1
’ to the Reset
CRCSCAN (RESET) bit in the CRCSCAN.CTRLA register will abort the error injection, just as
it would for an ordinary scan.