19.3.2.4 Voltage Regulator Monitor

SLPCTRL provides the control interface to the Voltage Regulator Monitor (VMON). VMON is an independent monitor for the on-chip voltage regulator. VMON will detect any voltage regulator failure and trigger a Machine Check Reset. VMON monitors the supply voltage when the device is in Active and Idle sleep modes.

The VMON Undervoltage Detected (VUV) flag and the VMON Overvoltage Detected (VOV) flag in the Interrupt Flags (INTFLAGS) register indicate if VMON has detected an under- or overvoltage condition, which is potentially a situation that never will be possible to observe since the reset controller ordinarily will reset the CPU if a VMON event condition occurs, and by doing so will reset the VUV and VOV flags. Such resets can be identified by the Machine Check Reset Flag (MCRF) flag in the Reset Flag Register (RSTCTRL.RSTFR) register and Voltage Regulator Monitor has Tripped (VREG) flag in the Machine Check Flags A (RSTCTRL.MCFLAGSA) register in the Reset Controller. For this reason, the VUV and VOV flags can be considered a redundant mechanism to catch failure modes in case the reset controller does not work as intended. These flags will also be set by fault injection. See the Fault Injection section for details.

VMON will, by default, monitor the voltage in sleep modes, which increases power consumption. Writing the VMON Sleep Mode Enable (VMONSEN) bit in the Voltage Regulator Control (VREGCTRL) register to ‘0’ will disable VMON in Power-Down sleep mode, reducing power consumption but disabling the safety mechanism.

Some sleep modes may cause the voltage regulator to reduce its output voltage to reduce power consumption. The VMON will automatically alter its detection window to match the voltage regulator output target level. The VMON is in Sleep Mode (VSLP) flag in the Interrupt Flags (INTFLAGS) register indicates whether the VMON window has been shifted to match a reduced voltage regulator output voltage.

Note: The VSLP flag in the INTFLAGS register will be permanently set when selecting OSC32K as the main clock source with UPDI inactive. Configure the Error Controller so that this does not cause an unwanted response, such as entering a safe state. If the VSLP flag is set outside a sleep mode, a hardware error has occurred, or OSC32K is the only active clock source.