23.4.2.4.5 Single-Slope PWM Operation

For single-slope PWM generation, the period time (T) is controlled by the TOP value set in the Period Value bit field in the Period register (PER.PER), and the Compare/Capture value in the Compare/Capture Channel n register (CCn.CC) controls the duty cycle of the generated waveform output. When up-counting, WO[n] is set at the start or on a compare match between the COUNT and TOP values, and cleared on a compare match between COUNT and CCn.CC. When down-counting, the WO[n] is cleared at the start or on a compare match between COUNT and ZERO, and set on compare match between COUNT and CCn.CC.

The following equation calculates the exact resolution for a single-slope PWM (R_{PWM_SS}) waveform: 

R_{PWM_SS} = \frac{log(TOP+1)}{log(2)}

The PWM frequency depends on the PER value and the peripheral clock frequency (f_{GCLK_TCC}), and can be calculated by the following equation:

f_{PWM_SS} = \frac{f_{GCLK_TCC}}{N(TOP+1)}

Where N represents the prescaler divider used (1, 2, 4, 8, 16, 64, 256, 1024).