23.4.2.4.6 Dual-Slope PWM Generation

For dual-slope PWM generation, the period time (T) is controlled by the TOP value set in the Period value bit field in the Period register (PER.PER), and the Compare/Capture Value in the Compare/Capture Channel n register (CCn.CC) controls the duty cycle of the generated waveform output. The figure below shows how the counter repeatedly counts from ZERO to TOP and then from TOP to ZERO. The waveform generator output is set on compare match when up-counting and cleared on a compare match when down-counting. An interrupt and/or event is generated on TOP (when counting upwards) and/or ZERO (when counting up or down).

In DSBOTH operation, the circular buffer must be enabled to enable the update condition on TOP.

Figure 23-8. Dual-Slope Pulse Width Modulation

Using dual-slope PWM results in a lower maximum operation frequency compared to single-slope PWM generation. The period (TOP) defines the PWM resolution. The minimum resolution is 1 bit (TOP=0x00000001).

The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):

RPWM_DS=log(TOP+1)log(2).

The PWM frequency fPWM_DS depends on the period setting (TOP) and the peripheral clock frequency fGCLK_TCC, and can be calculated by the following equation (outside of DSBOTH mode):

fPWM_DS=fGCLK_TCC2N⋅TOP

N represents the prescaler divider used. The waveform generated will have a maximum frequency of half the TCC clock frequency (fGCLK_TCC) when TOP is set to 0x00000001 and no prescaling is used.

The pulse width (PPWM_DS) depends on the CCn.CC value and the peripheral clock frequency (fGCLK_TCC), and can be calculated by the following equation:

PPWM_DS=2N⋅(TOP − CCx)fGCLK_TCC

N represents the prescaler divider used.

Note: In DSTOP, DSBOTTOM and DSBOTH operation, when TOP is lower than MAX/2, the MSB bit of CCn.CC defines the ramp on which the CCn Match interrupt or event is generated (rising if CCn[MSB] = 0, falling if CCn[MSB] = 1.)