23.4.2.4.1 Waveform Output Generation Operations

The compare channels can be used for waveform generation on output port pins. To make the waveform available on the connected pin, the following requirements must be fulfilled:

Choose a waveform generation mode by writing to the Waveform Generation Operation bit in the Waveform register (WAVE.WAVEGEN).
Optionally, invert the waveform output WO[x] by writing to the corresponding Waveform Output x Inversion bit in the Driver Control register (DRVCTRL.INVENx).
Configure the pins with the I/O Pin Controller. Refer to the PORT - I/O Pin Controller section for details.

Note: The MCx event must not be used when the compare channel is set in waveform output operating mode, except when it is used as a non-recoverable fault input.

The counter value is continuously compared with each CCn value. On a compare match, the Match or Capture Channel x bit in the Interrupt Flag Status and Clear register (INTFLAG.MCx) will be set on the next zero-to-one transition of CLK_TCC_COUNT (see Normal Frequency Operation). An interrupt and/or event can be generated under the same condition if a match or capture occurs, that is if the Match or Capture Channel x Interrupt Enable bit in the interrupt Enable Set register (INTENSET.MCx) and/or the Match or Capture Channel x Event Output Enable bit in the Event Control register (EVCTRL.MCEOx) is set to '1'. Both an interrupt and an event can be generated simultaneously. The same condition also generates a DMA request.

There are seven waveform configurations for the Waveform Generation Operation bit field in the Waveform register (WAVE.WAVEGEN). This will influence how the waveform is generated and impose restrictions on the top value. The configurations are:

Normal Frequency (NFRQ)
Match Frequency (MFRQ)
Normal Pulse-Width Modulation (NPWM)
Dual-slope, interrupt/event at TOP (DSTOP)
Dual-slope, interrupt/event at ZERO (DSBOTTOM)
Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)

When using the MFRQ configuration, the TOP value is defined by the CC0 register value. For the other waveform operations, the TOP value is defined by the Period (PER) register value.

For dual-slope waveform operations, the update occurs when the counter reaches ZERO. For the other waveform generation modes, the update occurs on counter wraparound, overflow, underflow, or retrigger.

The following table shows the update counter and overflow event/interrupt generation conditions in different operation modes.

Table 23-3. Counter Update and Overflow Event/interrupt Conditions
Name	Operation	TOP	Update	Output Waveform		OVFIF/Event
				On Match	On Update	Up	Down
NFRQ	Normal Frequency	PER	TOP/ ZERO	Toggle	Stable	TOP	ZERO
MFRQ	Match Frequency	CC0	TOP/ ZERO	Toggle	Stable	TOP	ZERO
NPWM	Single-slope PWM	PER	TOP/ ZERO	See section 'Output Polarity' below		TOP	ZERO
DSCRITICAL	Dual-slope PWM	PER	ZERO			-	ZERO
DSBOTTOM	Dual-slope PWM	PER	ZERO			-	ZERO
DSBOTH	Dual-slope PWM	PER	TOP⁽¹⁾ & ZERO			TOP	ZERO
DSTOP	Dual-slope PWM	PER	ZERO			TOP	–
Note: The UPDATE condition on TOP will only occur when the circular buffer is enabled for the channel. Refer to the Circular Buffer section for details.