37.9.2 External 32 kHz Crystal Oscillator (XOSC32K) Electrical Specifications

Table 37-14. 32.768 kHz Crystal Oscillator (XOSC32K) Electrical Specifications
Standard operating conditions: VDDIO = AVDD = 1.8V to 5.5V (Unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial

Param. No.SymbolCharacteristicsMin.Typ.Max.UnitsConditions
XOSC32_1fOSC_XOSC32XOSC32 crystal oscillator frequency—32.768—kHz —
XOSC32_3CXIN32XOSC32 XIN32 parasitic pin capacitance—3.5—pF —
XOSC32_5CXOUT32XOSC32 XOUT32 parasitic pin capacitance—3.6—pF—
XOSC32_11CLOAD_X32 (2) 32.768 kHz crystal load capacitance——9pFXOSC32KCTRL.LPMODE = 1

XOSC32KCTRL.XTALEN = 1

XOSC32KCTRL.ENABLE = 1
XOSC32_12——12.5pFXOSC32KCTRL.LPMODE = 0

XOSC32KCTRL.XTALEN = 1

XOSC32KCTRL.ENABLE = 1
XOSC32_13ESRX32 32.768 kHz crystal ESR——35kΩXOSC32KCTRL.LPMODE = 1

XOSC32KCTRL.XTALEN = 1

XOSC32KCTRL.ENABLE = 1

XOSC32_14——70kΩXOSC32KCTRL.LPMODE = 0

XOSC32KCTRL.XTALEN = 1

XOSC32KCTRL.ENABLE = 1
XOSC32_15TOSC32TOSC32 = 1/fOSC_XOSC32—30.5176—µs

See parameter XOSC32_1 for FOSC_XOSC32 value

XOSC32_17XOSC32ST(1)XOSC32 Crystal Star-up Time —51500(3)TOSCXOSC32KCTRL.LPMODE = 1

Crystal stabilization time only not oscillator ready

XOSC32_18—5800(3)TOSCXOSC32KCTRL.LPMODE = 0

Crystal stabilization time only not oscillator ready

XOSC32_19fOSC_XCLK32Ext clock oscillator input freq (XIN32 pin)—32.768—kHzXOSC32KCTRL.XTALEN = 0
XOSC32_21XCLK32DCExt clock oscillator duty cycle—50—%XOSC32KCTRL.XTALEN = 0
XOSC32_23XCLK32FSTXIN32 clock fail safe time-out period—4 x TOSC32(4)—µs —
Note:
  1. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitics that are outside the scope of this specification. If this is a major concern the customer would need to characterize this based on their design choices.
  2. CRYSTAL LOAD CAPACITOR CALCULATION GIVEN:
    • Standard PCB trace capacitance = 1.5 pF per 12.5 mm (0.5 inches) (i.e. PCB STD TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
    • Xtal PCB capacitance typical therefore ~= 2.5 pF for a tight PCB xtal layout
    • For CXIN and CXOUT within 4pF of each other, assume CXTAL_EFF = ((CXIN + CXOUT)/2)
      Note: Averaging CXIN and CXOUT will affect final calculated CLOAD value by less than the tolerance of the capacitor selection.

    EQUATION 1:

    MFG CLOAD Spec = {( [CXIN + C1] x [CXOUT + C2] )/[CXIN + C1 + C2 + CXOUT] } + estimated oscillator PCB stray capacitance

    • Assuming C1 = C2 and CXIN ~= CXOUT, the formula can be further simplified and restated to solve for C1 and C2 by:

    EQUATION 2: (Simplified Equation 1)

    C1 = C2 = ((2 x MFG CLOAD spec) - CXTAL_EFF - (2 x PCB capacitance))

    EXAMPLE ONLY:

    • XTAL Mfg CLOAD Data Sheet Spec = 12 pF
    • PCB XTAL trace Capacitance = 2.5 pF
    • CXIN pin = 6.5 pF, CXOUT pin = 4.5 pF. Therefore CXTAL_EFF = ((CXIN + CXOUT)/2)

    CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5 pF

    C1 = C2 = ((2 x MFG CLOAD spec) - CXTAL_EFF - (2 x PCB capacitance))

    C1 = C2 = (24 - 5.5 - (2 x 2.5))

    C1 = C2 = (24 - 5.5 - 5)

    C1 = C2 = 13.5 pF (Always rounded down)

    C1 = C2 = 13 pF (i.e., for hypothetical example crystal external load capacitors)

    User C1 = C2 = 13 pF ≤ CLOAD_X32 (max) spec

    Figure 37-1. XTAL
  3. User Selectable in XOSC32KCTRL.CSUT[1:0].
  4. Period of four safe clocks, monitored the Clock Failure Detection watching for XOSC32K clock activity.