13.4.7.2.1 Frequency Drift Detection

The captured count value enters the comparator logic block, and its value is simultaneously compared against the contents of four limit registers. This essentially forms four independent thresholds confining the monitored clock frequency’s deviation into two acceptable ranges defined by two pairs of high/low limit registers. Monitored clock frequency drift is, therefore, detectable per user-defined tolerance. Upon detection of a threshold violation, the user is notified via an interrupt event.