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dsPIC33AK512MPS512 Family Data Sheet
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15
CAN Flexible Data-Rate (FD) Protocol Module
15.5
Modes of Operation
15.5.3
Normal Modes
Operating Conditions
High-Performance dsPIC33A DSP/RISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Controller Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512
Family Features
Pin Diagrams
1
Pinout I/O Descriptions
2
Device Overview
3
Guidelines for Getting Started with Digital Signal Controllers
4
CPU
5
Memory Organization
6
Data Memory
7
Flash Program Memory
8
Configuration Bits
9
Security Module
10
Resets
11
Interrupt Controller
12
I/O Ports with Edge Detect
13
Oscillator Module
14
Direct Memory Access (DMA) Controller
15
CAN Flexible Data-Rate (FD) Protocol Module
15.1
Device-Specific Information
15.2
Features
15.3
CAN FD Message Frames
15.4
Register Summary
15.5
Modes of Operation
15.5.1
Mode Change
15.5.2
Configuration Mode
15.5.3
Normal Modes
15.5.3.1
Normal CAN FD Mode
15.5.3.2
Normal CAN 2.0 Mode
15.5.4
Disable Mode
15.5.5
Debug Modes
15.5.6
Low-Power Modes
15.6
Configuration
15.7
Message Transmission
15.8
Transmit Event FIFO - TEF
15.9
Message Filtering
15.10
Message Reception
15.11
FIFO Behavior
15.12
Timestamping
15.13
Interrupts
15.14
Error Handling
16
High-Resolution PWM with Fine Edge Placement
17
40 MSPS Analog-to-Digital Converter (ADC)
18
Effects of Reset
19
Integrated Touch Controller (ITC)
20
High-Speed Analog Comparator with Slope Compensation DAC
21
Quadrature Encoder Interface (QEI)
22
Universal Asynchronous Receiver Transmitter (UART)
23
Serial Peripheral Interface (SPI)
24
Inter-Integrated Circuit (I
2
C)
25
Single-Edge Nibble Transmission (SENT)
26
Bidirectional Serial Synchronous (BiSS) Module
27
Timers
28
Capture/Compare/PWM/Timer Modules (SCCP/MCCP)
29
Configurable Logic Cell (CLC)
30
Peripheral Trigger Generator (PTG)
31
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
32
Current Bias Generator (CBG)
33
UREF Reference Output
34
Operational Amplifier (Op Amp)
35
Watchdog Timer (WDT)
36
Deadman Timer (DMT)
37
Device Power-Saving Modes
38
JTAG Interface
39
In-Circuit Debugger
40
Instruction Set Summary
41
Development Support
42
Electrical Characteristics
43
Packaging Information
44
Revision History
45
Product Identification System
Microchip Information
15.5.3 Normal Modes
