24.5.2.2.5 TBF Status Flag
When transmitting, the TBF status bit (I2CxSTAT1[0]) is set when the CPU writes to the I2CxTRN register and is cleared when all eight bits are shifted out.
When transmitting, the TBF status bit (I2CxSTAT1[0]) is set when the CPU writes to the I2CxTRN register and is cleared when all eight bits are shifted out.