3.5.1 PCIe AXI Master IF Throughput

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Throughput calculation is carried out at 250 MHz AXI CLK using built-in DMA (64 KB of DMA size), maximum payload of 128 Bytes. The built-in DMA initiates 32-bit AXI burst length transactions on AXI Master IF. When using the built-in DMA, eight PCIe outstanding transactions are supported.

Table 3-9. PCIe AXI Master IF Throughput
Link Width	Link Speed	PC to LSRAM (Memory Read from PC)		LSRAM to PC (Memory Write  to PC)		Maximum Theoretical Throughput (MBps)
Link Width	Link Speed	Maximum Throughput (MBps)	% of Theoretical Throughput	Throughput (MBps)	% of Theoretical Throughput	Maximum Theoretical Throughput (MBps)
x1	Gen1	206	82.4	226	90.4	250
x1	Gen2	411	82.2	453	90.6	500
x2	Gen1	410	82	439	87.8	500
x2	Gen2	814	81.4	875	87.5	1000
x4	Gen1	811	81.1	830	83	1000
x4	Gen2	1181	59.05	1508	75.4	2000