1.6 PCIESS Port List

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The PCIESS block is generated using the Libero PCIe Configurator. The generation of the PCIESS block includes ports based on the PCIe Configurator settings. The following table lists the port descriptions. The PCIESS also has several status signals, interrupt signals, and power management signals available to the FPGA fabric.

Table 1-3. PCIESS Port List¹^, ²
Port Name	Direction	Description
AXI_CLK	Input	Global AXI clock. Shared for both PCIESS interfaces.
AXI_CLK_STABLE	Input	Clock lock signal. Indicates that the AXI_CLK source from the fabric is locked and ready for use.
Master
PCIESS_AXI_#_M_ARADDR[31:0]	Output	Read address. The address of the first transfer in a read burst transaction.
PCIESS_AXI_#_M_ARBURST[1:0]	Output	Read burst type. The burst type and the size details determine how the address for each transfer within the burst is calculated.
PCIESS_AXI_#_M_ARID[3:0]	Output	Read address ID. Identification tag for the read address group of signals.
PCIESS_AXI_#_M_ARLEN[7:0]	Output	Burst length. Indicates the exact number of transfers in a burst.
PCIESS_AXI_#_M_ARREADY	Input	Read address ready. Indicates that the slave is ready to accept an address and associated control signals.
PCIESS_AXI_#_M_ARSIZE[2:0]	Output	Burst size. Indicates the size of each transfer in the burst.
PCIESS_AXI_#_M_ARVALID	Output	Read address valid. Indicates that the channel is signaling valid read address and control information.
PCIESS_AXI_#_M_AWADDR[31:0]	Output	Write address. The address of the first transfer in a write burst transaction.
PCIESS_AXI_#_M_AWBURST[1:0]	Output	Write burst type. The burst type and the size of information determine how the address for each transfer within the burst is calculated.
PCIESS_AXI_#_M_AWID[3:0]	Output	Write address ID. Identification tag for the write address group of signals.
PCIESS_AXI_#_M_AWLEN[7:0]	Output	Burst length. Indicates the exact number of transfers in a burst, which determines the number of data transfers associated with the address.
PCIESS_AXI_#_M_AWREADY	Input	Write address ready. Indicates that the slave is ready to accept an address and associated control signals.
PCIESS_AXI_#_M_AWSIZE[2:0]	Output	Burst size. Indicates the size of each transfer in the burst.
PCIESS_AXI_#_M_AWVALID	Output	Write address valid. Indicates that the channel is signaling valid write address and control information.
PCIESS_AXI_#_M_BID[3:0]	Input	Response ID tag. Identification tag for the write response.
PCIESS_AXI_#_M_BREADY	Output	Response ready. Indicates that the master is ready to accept a write response.
PCIESS_AXI_#_M_BRESP[1:0]	Input	Write response. Indicates the status of the write transaction. When it is asserted to 2'b10 (SLVERR/DECERR), unsupported request to PCIe is reported.
PCIESS_AXI_#_M_BVALID	Input	Write response valid. Indicates that the channel is signaling a valid write response.
PCIESS_AXI_#_M_RDATA[63:0]	Input	Read data.
PCIESS_AXI_#_M_RID[3:0]	Input	Read ID tag. Identification tag for the read data group of signals generated by the slave.
PCIESS_AXI_#_M_RLAST	Input	Read last. Indicates the last transfer in a read burst.
PCIESS_AXI_#_M_RREADY	Output	Read ready. Indicates that the master can accept the read data and associated control signals, along with response information.
PCIESS_AXI_#_M_RRESP[1:0]	Input	Read response. Indicates the status of the read transfer. When it is asserted to 2'b10(SLVERR), completion with Unsupported Request status is returned. When it is asserted to 2'b11(DECERR), completion with Completion Abort status is returned.
PCIESS_AXI_#_M_RVALID	Input	Read valid. Indicates that the channel is signaling the required read data.
PCIESS_AXI_#_M_WDATA[63:0]	Output	Write data.
PCIESS_AXI_#_M_WLAST	Output	Write last. Indicates the last transfer in a write burst.
PCIESS_AXI_#_M_WREADY	Input	Write ready. Indicates that the slave can accept the write data.
PCIESS_AXI_#_M_WSTRB[7:0]	Output	Write strobes. Indicates the byte lanes that hold valid data. There is one write strobe bit for every eight bits of the write data bus.
PCIESS_AXI_#_M_WVALID	Output	Write valid. Indicates that valid write data and strobes are available.
Slave
PCIESS_AXI_#_S_ARADDR[31:0]	Input	Read address. The address of the first transfer in a read burst transaction.
PCIESS_AXI_#_S_ARBURST[1:0]	Input	Burst type. The burst type and the size of information determine how the address for each transfer within the burst is calculated.
PCIESS_AXI_#_S_ARID[3:0]	Input	Read address ID. Identification tag for the read address group of signals.
PCIESS_AXI_#_S_ARLEN[7:0]	Input	Burst length. Indicates the exact number of transfers in a burst.
PCIESS_AXI_#_S_ARREADY	Output	Write address ready. Indicates that the slave is ready to accept an address and the associated control signals.
PCIESS_AXI_#_S_ARSIZE[2:0]	Input	Burst size. Indicates the size of each transfer in the burst.
PCIESS_AXI_#_S_ARVALID	Input	Read address valid. Indicates that the channel is signaling valid read address and control information.
PCIESS_AXI_#_S_AWADDR[31:0]	Input	Write address. Address of the first transfer in a write burst transaction.
PCIESS_AXI_#_S_AWBURST[1:0]	Input	Burst type. The burst type and the size information determine how the address for each transfer within the burst is calculated.
PCIESS_AXI_#_S_AWID[3:0]	Input	Write address ID. Identification tag for the write address group of signals.
PCIESS_AXI_#_S_AWLEN[7:0]	Input	Burst length. Indicates the exact number of transfers in a burst, which determines the number of data transfers associated with the address.
PCIESS_AXI_#_S_AWREADY	Output	Write address ready. Indicates that the slave is ready to accept an address and associated control signals.
PCIESS_AXI_#_S_AWSIZE[2:0]	Input	Burst size. Indicates the size of each transfer in the burst.
PCIESS_AXI_#_S_AWVALID	Input	Write address valid. Indicates that the channel is signaling valid write address and control information.
PCIESS_AXI_#_S_BID[3:0]	Output	Response ID tag. Identification tag for the write response.
PCIESS_AXI_#_S_BREADY	Input	Response ready. Indicates that the master can accept a write response.
PCIESS_AXI_#_S_BRESP[1:0]	Output	Write response. Indicates the status of the write transaction. It is asserted to 2'b10(SLVERR), when: An AXI Write Completion Timeout (128 ms in hardware and 128 µs in simulation) cannot be transferred to the PCIe link due to an AXI write transaction, because the link is down or in low-power mode. ECRC error occurs in TLP/Poisoned TLP. It is asserted to 2'b11(DECERR) when no address translation table is matched (Unsupported Address).
PCIESS_AXI_#_S_BVALID	Output	Write response valid. Indicates that the channel is signaling a valid write response.
PCIESS_AXI_#_S_RDATA[63:0]	Output	Read data.
PCIESS_AXI_#_S_RID[3:0]	Output	Read ID tag. Identification tag for the read data group of signals generated by the slave.
PCIESS_AXI_#_S_RLAST	Output	Read last. Indicates the last transfer in a read burst.
PCIESS_AXI_#_S_RREADY	Input	Read ready. Indicates that the master can accept the read data and response information.
PCIESS_AXI_#_S_RRESP[1:0]	Output	Read response. Indicates the status of the read transfer. It is asserted to 2'b10(SLVERR), when: PCIe Completion TLP with Unsupported Request (UR) Status ECRC error/Poisoned TLP occurs. It is asserted to 2'b11(DECERR), when: No address translation table is matched (Unsupported Address) PCIe Completion TLP with Completer Abort (CA) status
PCIESS_AXI_#_S_RVALID	Output	Read valid. Indicates that the channel is signaling the required read data.
PCIESS_AXI_#_S_WDATA[63:0]	Input	Write data.
PCIESS_AXI_#_S_WLAST	Input	Write last. Indicates the last transfer in a write burst.
PCIESS_AXI_#_S_WREADY	Output	Write ready. Indicates that the slave can accept the write data.
PCIESS_AXI_#_S_WSTRB[7:0]	Input	Write strobes. Indicates the byte lanes that hold valid data. There is one write strobe bit for each eight bits of the write data bus.
PCIESS_AXI_#_S_WVALID	Input	Write valid. Indicates that valid write data and strobes are available.
PCIe
PCIE_#_M_RDERR	Input	Tie to 0
PCIE_#_M_WDERR	Output	Not connected
PCIE_#_S_RDERR	Output	Not connected
PCIE_#_S_WDERR	Input	Tie to 0
PCIE_#_HOT_RST_EXIT	Output	Hot reset exit. Asserted for one clock cycle when the LTSSM exits Hot Reset state. Prompts the application layer to perform a global reset.
PCIE_#_DLUP_EXIT	Output	DL-up exit. Indicates transition from DL_UP to DL_DOWN. dlup_exit = 1'b0, data link layer is down dlup_exit = 1'b1, data link layer is up only valid when LTSSM is in L0 state
PCIE_#_INTERUPT[7:0]	Input	Local interrupt input ports. The fabric logic can drive up to eight interrupt sources by generating a pulse (high) on the ports and the clock pluses are asserted. [7:0] can be used for MSI. [0] is also available for INTx. Used only for endpoints. PCIESS uses TL_CLK to monitor this signal. MSI offsets are [negotiated interrupt-1:negotiated interrupt-8]
PCIE_#_INTERUPT_OUT	Output	Local interrupt output port. Indicates that one of the possible interrupt sources was detected and the user can read the interrupt through the DRI. It is a level sensitive signal; whenever an interrupt described in ISTATUS_LOCAL, SEC_ERROR_INT register, DED_ERROR_INT register, and PCIE_EVENT_INT register is active, the PCIE_#_INTERUPT_OUT signal gets asserted and remains high. It is low when the corresponding interrupts in the registers are cleared.
PCIE_#_LTSSM[4:0]	Output	LTSSM state encoding: 0x0: LTSSM_DET_QUIET 0x1: LTSSM_DET_ACT 0x2: LTSSM_POL_ACT 0x3: LTSSM_POL_COMP 0x4: LTSSM_POL_CFG 0x5: LTSSM_CFG_LWSTR 0x6: LTSSM_CFG_LWACC 0x7: LTSSM_CFG_LWAIT 0x8: LTSSM_CFG_LNACC 0x9: LTSSM_CFG_CPLT 0xa: LTSSM_CFG_IDLE 0xb: LTSSM_RCV_RLOCK 0xc: LTSSM_RCV_EQL 0xd: LTSSM_RCV_SPEED 0xe: LTSSM_RCV_RCFG 0xf: LTSSM_RCV_IDLE 0x10: LTSSM_L0 0x11: LTSSM_L0S 0x12: LTSSM_L1_ENTRY 0x13: LTSSM_L1_IDLE 0x14: Reserved 0x15: Reserved 0x16: LTSSM_DISABLED 0x17: LTSSM_LOOPBACK_ENTRY 0x18: LTSSM_LOOPBACK_ACTIVE 0x19: LTSSM_LOOPBACK_EXIT 0x1a: LTSSM_HOTRESET
PCIE_#_PERST_N	Input	Asynchronous. PERST_N can use any GPIO.
PCIE_#_TL_CLK_125MHz	Input	125 MHz (maximum) clock input. Continuous running clock is required for PCIe core transaction layer. Connects to the DIV_CLK output from the TX_PLL. TL_CLK is available only after PCIe initialization. User have to derive from the on-chip oscillator to drive the TL_CLK during PCIe initialization. An NGMUX can be used to switch this clock to the required DIV_CLK after PCIe initialization. For information about PolarFire FPGA reference design, see PolarFire FPGA PCIe EndPoint DDR3L DDR4 Memory Controller Data Plane. For information about PolarFire SoC FPGA Linux reference design, see GitHub.
Transceiver
CLKS_FROM_TXPLL_TO_PCIE_#	Input	PCIE_#_TX_BIT_CLK_#: This port must be driven by the BIT_CLK output of the Tx PLL. Gen1 2.5 G, Gen2 5 G, and mix of Gen 1 and Gen 2 is 2.5 G.
		PCIE_#_TX_PLL_REF_CLK_#: Reference clock from TX_PLL.
		PCIE_#_TX_PLL_LOCK_#: Lock status input to PCIESS. Connects to the lock output of the TX_PLL.
PCIESS_LANE#_CDR_REF_CLK_#	Input	Reference clock to lane CDR. Connects to the REF_CLK input of the TX_PLL.
PCIESS_LANE_TXDn_P	Output	Transceiver differential output transmit data. n = 0, 1, 2, 3.
PCIESS_LANE_TXDn_N	Output
PCIESS_LANE_RXDn_P	Output	Transceiver differential input receive data. n = 0, 1, 2, 3.
PCIESS_LANE_RXDn_N	Output
Note: Unless otherwise indicated, all signals are active-high. # = 0, 1.