1.2 Data-link and Transaction Layers

The PCIe DL and TL includes:

  • PCIe controller
    • Lane reversal
    • Link training and status state machine (LTSSM)
    • Electrical idle generation
    • Receiver detection
    • TS1/TS2 generation/detection
  • PCIe transmit/receive interface between the PCIe bridge and PCIe controller
  • PCIe configuration interface providing the bridge access to the PCIe configuration space
  • PCIe miscellaneous interface to allow the bridge access to manage low-power and interrupts

The PCIESS includes the data path from the transceiver to the user-defined application layer of the FPGA fabric. The AXI4 bridges the application layer to the transaction layer. The transaction layer communicates with the data-link layer through FIFOs. The data-link layer communicates with the physical layer through FIFOs. The data is then passed to the transaction layer blocks that manage read and write requests from the software. Finally, the data is passed to the application layer hosted in the FPGA fabric (Figure   1).

Data Link Layer – The data link layer (DL) is responsible for link management including transaction layer packet (TLP) acknowledgment (a retry mechanism in case of a non-acknowledged packet), flow control across the link (transmission and reception), power management, CRC generation and checking, error reporting, and logging. The DL verifies the packets sequence number and checks for errors. The DL ensures packet integrity, and adds a sequence number and Link Cyclic Redundancy Check (LCRC) to the packet.

The replay buffer located in the data link layer stores a copy of a transmitted TLP until the transmitted packet is acknowledged by the receive side of the link. Each stored TLP includes the header, an optional data payload (the maximum size of which is determined by the maximum payload size parameter), an optional end-to-end cyclic redundancy check (ECRC), the sequence number, and the link cyclic redundancy check (LCRC) field for transaction and data integrity. The replay buffer stores the read data payload from the AXI4 master and write data payload from the AXI4 slave.

Transaction Layer – The transaction layer is responsible for the transfer of transaction layer packets (TLP). The transaction layer disassembles the transaction and transfers data to the application layer in a form that it can recognize. The transaction layer generates a TLP from information sent by the application layer. This TLP includes a header and can also include a data payload. The application communicates to the PCIe link using AXI4 master and slave interface through bridge layer.