1.1 Physical Layer Interface

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A PCIe lane consists of a pair of differential transmit signals and a pair of differential receive signals. The lanes are organized, as listed in the following table.

Table 1-1. Lane Configuration
X1	X2	X4
PCIe0 (Lane0) and PCIe1 (Lane2)	PCIe0 (Lane0, Lane1) and  PCIe1 (Lane2, Lane3)	PCIe1 (Lane 0, Lane1, Lane2, and Lane3)

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