1.5 PCIESS Configuration Interface

Programmable FPGA Resources: The registers required for the initial configuration of the PCIESS are loaded based on the options selected in the Libero PCIESS Configurator wizard. On device power-up, these values are automatically loaded into the configuration registers from the on-chip non-volatile memory during the design initialization process. The design initialization uses the dedicated resources to bring up the PCIESS features at power-up or device reset. This does not require any programmable FPGA user resources. The PCIESS then reads and writes the configuration space registers as the link comes up and the endpoint device is enumerated into the host system.

PCIESS can be dynamically configured through the following interfaces:

• DRI – is used to configure transceiver lane registers.
• APB – is used to configure PCIe control registers.