36.8.5 SLCDC Status Register
| Name: | SLCDC_SR |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MAPFRZS | DFFRZS | ENA | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bit 7 – MAPFRZS Remapping Configuration Freeze Status
| Value | Description |
|---|---|
| 0 |
SLCDC_SMR can be written if SLCDC_WPMR.WPEN=0. |
| 1 |
SLCDC_SMR is locked until next VDDLCD power-up. |
Bit 6 – DFFRZS Display Panel Features Configuration Freeze Status
| Value | Description |
|---|---|
| 0 |
SLCDC_MR and SLCDC_FRR can be written if SLCDC_WPMR.WPEN=0. |
| 1 |
SLCDC_MR and SLCDC_FRR are locked until next VDDLCD power-up. |
Bit 0 – ENA Enable Status (Automatically Set/Reset)
| Value | Description |
|---|---|
| 0 | The SLCDC is disabled. |
| 1 | The SLCDC is enabled. |